Intel RS3SC008 Ficha de datos

Revision 3.1Intel® 82599 10 Gigabit Ethernet ControllerSpecification UpdateNetworking Division (ND)March 2014

Intel® 82599 10 GbE Controller—Hardware Sightings, Clarifications, Changes, Updates, andErrata10 2.0 Hardware Sightings, Clarifications, Chang

11Hardware Sightings, Clarifications, Changes, Updates, and Errata—Intel® 82599 10 GbE Controller 16. SR-IOV Prefetchable Address Space N/ATab

Intel® 82599 10 GbE Controller—Hardware Sightings, Clarifications, Changes, Updates, andErrata12 8. Incorrect Behavior in the Switch Security V

13Hardware Sightings, Clarifications, Changes, Updates, and Errata—Intel® 82599 10 GbE Controller 30. NC-SI: Additional Multicast Packets May B

Intel® 82599 10 GbE Controller—Hardware Sightings, Clarifications, Changes, Updates, andErrata14 53. Flow Director Filters Configuration Issue

15Specification Clarifications—Intel® 82599 10 GbE Controller2.1 Specification Clarifications1 SFP+ StatementIt is important to note that t

Intel® 82599 10 GbE Controller—Specification Clarifications16 4 Use of Wake on LAN Together with ManageabilityThe Wakeup Filter Control Regist

17Specification Clarifications—Intel® 82599 10 GbE Controller6 AN 1G TIMEOUT Only Works When the Link Partner Is IdleThe auto-negotiation ti

Intel® 82599 10 GbE Controller—Specification Clarifications18 9 Master Disable FlowDuring the “Master Disable” flow, the device driver should

19Specification Clarifications—Intel® 82599 10 GbE Controller13 82599 SFP+ Receiver Specification Conforms to SFF-8431The 82599 SFI interface

Intel® 82599 10 GbE Controller—Revision History2 Revision HistoryDate Revision Description9/2008 0.5• Supports datasheet. Initial public release

Intel® 82599 10 GbE Controller—Specification Changes20 2.2 Specification Changes1 PBA Number Module — Word Address 0x15-0x16Note: This infor

21Specification Changes—Intel® 82599 10 GbE Controller5 MAC Link Setup and Auto NegotiationAccording to the 82599 Datasheet (see Section 3.7.

Intel® 82599 10 GbE Controller—Documentation Updates22 8 EEPROM Device SizeThe following EEPROM device size updates will be included in the ne

23Errata—Intel® 82599 10 GbE Controller2.4 ErrataNote: If the errata applies to a stepping, “Yes” is indicated for the stepping (for example:

Intel® 82599 10 GbE Controller—Errata24 Workaround:Software - Reset Flow Director (FD) tables when max-length indication is observed, or hold im

25Errata—Intel® 82599 10 GbE Controller5 Flow Director Statistics InaccuracyProblem:FDIRMATCH should count the number of packets that matched

Intel® 82599 10 GbE Controller—Errata26 8 Incorrect Behavior in the Switch Security Violation Packet Count (SSVPC) Statistic RegisterProblem:D

27Errata—Intel® 82599 10 GbE ControllerWorkaround:SW - in 100 Mb/s link mode we need to disable aggregation in DMA-Rx (set RDRXCTL.AGGDIS=1) an

Intel® 82599 10 GbE Controller—Errata28 13 Issues in Clock Switching of MAC ClocksProblem:During changes in the internal link-speed, the timin

29Errata—Intel® 82599 10 GbE Controller15 Clause 37 AN: 82599 Will not Restart AN if Receiving Invalid Idle Codes During Configuration StateP

3Revision History—Intel® 82599 10 GbE Controller8/15/2011 2.81Specification Clarifications added or updated:• 6. AN 1G TIMEOUT Only Works When

Intel® 82599 10 GbE Controller—Errata30 18 SGMII 100M: 82599 Might Need a SW-Reset When Link-Mode Enters/Exits 100MProblem:On speed changes to

31Errata—Intel® 82599 10 GbE ControllerWorkaround:Operate in BYPASS mode and avoid any 82599 output contention.Status: B0=Yes; NoFix21 MACSec

Intel® 82599 10 GbE Controller—Errata32 23 ERR_COR Message TLPs Are not Sent for Advisory Errors in D3Problem:If the 82599 is in D3 state, and

33Errata—Intel® 82599 10 GbE ControllerWorkaround:None.Status: B0=Yes; NoFix26 82599 Might not Be Recognized by PCIe in EEPROM-Less ModeProbl

Intel® 82599 10 GbE Controller—Errata34 28 Re-Enabling a Port Using the Rising Edge of LAN_DIS_N Requires a LAN_PWR_GOOD ResetProblem:To re-en

35Errata—Intel® 82599 10 GbE ControllerImplication:Additional packets might be forwarded to the BMC.Workaround:BMC should filter the different

Intel® 82599 10 GbE Controller—Errata36 33 The EEPROM Core Clocks Gate Disable Setting Impacts Link Status During D3 StateProblem:Setting EEPR

37Errata—Intel® 82599 10 GbE ControllerWorkaround:Keep a dummy Tx queue active in a reserved, lowest priority TC, transmitting packets that are

Intel® 82599 10 GbE Controller—Errata38 37 PCIe: PM_Active_State_NAK Message Might Be IgnoredProblem:A PM_Active_State_NAK message received by

39Errata—Intel® 82599 10 GbE Controller38 PCIe: Incorrect PCIe De-emphasis Level Might Be ReportedProblem:Current De-emphasis Level status bi

Intel® 82599 10 GbE Controller—Revision History4 9/5/2012 2.87Specification Clarifications added or updated:• 2. PCIe Completion Timeout Value M

Intel® 82599 10 GbE Controller—Errata40 Workaround:If a system is requested to operate under this specific scenario, a custom EEPROM image can b

41Errata—Intel® 82599 10 GbE Controller42 PCIe: 82599 Transmitter Does not Enter L0sProblem:According to the PCIe specification “Ports that a

Intel® 82599 10 GbE Controller—Errata42 44 Header Splitting Can Cause Unpredictable BehaviorProblem:Header Splitting mode (SRRCTL.DESCTYPE=010

43Errata—Intel® 82599 10 GbE Controller46 PCIe: Correctable Errors Reported When Using Rx L0s in a x1 ConfigurationProblem:When using Rx L0s

Intel® 82599 10 GbE Controller—Errata44 48 FCoE: Exhausted Receive Context Is not Invalidated if Last Buffer Size Is Equal to User Buffer Size

45Errata—Intel® 82599 10 GbE Controller49 KR TXFFE Coefficient Update Is not Possible if Middle Coefficient Is at Maximum ValueProblem:During

Intel® 82599 10 GbE Controller—Errata46 51 LEDs Cannot Be Configured to Blink in LED_ON ModeProblem:When the LEDx_Mode field of a specific LED

47Errata—Intel® 82599 10 GbE ControllerWorkaround:If RXCTRL.RXEN is clear, set SECRXCTL.RX_DIS and wait for a SECRXSTAT.SECRX_RDY indication be

Intel® 82599 10 GbE Controller—Errata48 Workaround:This issue is resolved by the 82599 EEPROM Dev Starter rev 4.22 or newer. Status: B0=Yes; NoF

49Errata—Intel® 82599 10 GbE Controller58 82599 LAN Port #1 SFI Link InstabilityProblem:If the PCIe Function #0 is moved to D3 state, it migh

5LEGAL—Intel® 82599 10 GbE ControllerLEGALBy using this document, in addition to any agreements you have with Intel, you accept the terms set

Intel® 82599 10 GbE Controller—Errata50 60 IPv4 Checksum Error Might Be Reported for Multicast Frames Over 12 KBProblem:IPE (IPv4 Checksum Err

51Errata—Intel® 82599 10 GbE Controller62 Flow Director: Collision Indication Can Be Cleared by Adding a New FilterProblem:A Flow Director co

Intel® 82599 10 GbE Controller—- Software Clarifications52 3.0 - Software Clarifications1 While in TCP Segmentation Offload, Each Buffer Is

53- Software Clarifications—Intel® 82599 10 GbE Controller3 Serial Interfaces Programmed by Bit BangingWhen bit-banging on a serial interface

Intel® 82599 10 GbE Controller—- Software Clarifications54 NOTE: This page intentionally left blank.

Intel® 82599 10 GbE Controller—LEGAL6 NOTE: This page intentionally left blank.

7Introduction—Intel® 82599 10 GbE Controller1.0 IntroductionThis document applies to the Intel® 82599 10 GbE Controller.This document is an u

Intel® 82599 10 GbE Controller—Marking Diagram8 1.2 Marking Diagram Lead-free parts will have “JL” as the prefix for the product code .The “S”

9Nomenclature Used in This Document—Intel® 82599 10 GbE Controller1.3 Nomenclature Used in This DocumentThis document uses specific terms, co