Intel Computer Hardware 80200 Manual de usuario descargar pdf (Pagina 62)

1 2 ... 57 58 59 60 61 62 63 64 65 66 67 ... 288 289

80200 Processor based on 1
Microarchitecture 1
Contents 3
A Compatibility: Intel 9
Introduction 17
1.1.2 Features 18
1.2.1 Number Representation 21
1.3 Other Relevant Documents 22
Programming Model 23
2.2.5 Base Register Update 24
2.3.1 DSP Coprocessor 0 (CP0) 25
2.3.2 New Page Attributes 31
2.3.4 Event Architecture 34
2.3.4.3 Prefetch Aborts 35
2.3.4.4 Data Aborts 36
Contents 38
Memory Management 39
3.2 Architecture Model 40
3.2.3 Exceptions 42
3.4 Control 44
3.4.3 Locking Entries 45
Instruction Cache 49
4.2 Operation 50
4.2.3 Fetch Policy 51
4.2.5 Parity Protection 52
4.3 Instruction Cache Control 54
Branch Target Buffer 59
5.1.1 Reset 60
5.1.2 Update Policy 60
5.2 BTB Control 61
Data Cache 63
6.2.3 Cache Policies 67
6.2.3.2 Read Miss Policy 68
6.2.3.3 Write Miss Policy 69
6.2.5 Parity Protection 70
6.2.6 Atomic Accesses 70
6.3.2 Enabling/Disabling 71
Bits Description Notes 81
7.2 CP15 Registers 82
7.2.5 Register 4: Reserved 87
• translation faults 89
• domain faults 89
• permission faults 89
7.3 CP14 Registers 98
Configuration 100
System Management 101
8.2 Processor Reset 103
8.2.2 Reset Effect on Outputs 104
8.3 Power Management 105
Interrupts 107
9.3 Programmer Model 108
9.3.1 INTCTL 109
9.3.2 INTSRC 110
9.3.3 INTSTR 111
External Bus 113
10.2 Signal Description 115
10.2.1 Request Bus 116
10.2.2 Data Bus 118
10.2.3 Critical Word First 119
10.2.4 Configuration Pins 120
10.2.5 Multimaster Support 121
10.2.6 Abort 123
10.2.7 ECC 124
10.3 Examples 126
10.3.4 Word Write 129
10.3.5.1 Write Burst 131
10.3.6 Write Burst, Coalesced 132
10.3.7 Pipelined Accesses 133
10.3.8 Locked Access 134
10.3.9 Aborted Access 135
10.3.10 Hold 136
Bus Controller 137
11.3 Error Handling 138
11.3.2 ECC Errors 139
11.4 Programmer Model 141
11.4.2 ECC Error Registers 145
Performance Monitoring 147
12.4.1 Managing PMNC 151
12.7 Examples 158
Software Debug 159
13.3 Introduction 160
13.4.1 Global Enable Bit (GE) 162
13.4.2 Halt Mode Bit (H) 162
13.4.4 Sticky Abort Bit (SA) 163
13.5 Debug Exceptions 164
13.5.2 Monitor Mode 166
13.6 HW Breakpoint Resources 167
13.6.2 Data Breakpoints 168
13.7 Software Breakpoints 169
13.8.2 Overflow Flag (OV) 172
13.8.3 Download Flag (D) 172
13.9 Transmit Register (TX) 174
13.10 Receive Register (RX) 174
13.11 Debug JTAG Access 175
13.11.2 SELDCSR JTAG Register 176
13.11.2.1 DBG.HLD_RST 177
13.11.3 DBGTX JTAG Command 178
13.11.4 DBGTX JTAG Register 179
13.11.5 DBGRX JTAG Command 179
13.11.6 DBGRX JTAG Register 180
13.11.6.1 RX Write Logic 181
13.11.6.2 DBGRX Data Register 182
13.11.6.3 DBG.RR 182
13.11.6.4 DBG.V 183
13.11.6.5 DBG.RX 183
13.11.6.6 DBG.D 183
13.11.6.7 DBG.FLUSH 183
13.12 Trace Buffer 184
13.13 Trace Buffer Entries 186
13.13.1.3 Address Bytes 189
13.13.2 Trace Buffer Usage 190
13.14.1 LDIC JTAG Command 192
13.14.3 LDIC Cache Functions 194
Debugger Actions 201
Debug Handler Actions 201
• a debug handler; 205
• External memory 209
13.15.2.4 High-Speed Download 210
• turn off all breakpoints; 211
• invalidate the btb; 211
Performance Considerations 213
14.2 Branch Prediction 214
14.3 Addressing Modes 214
14.4 Instruction Latencies 215
• Minimum Resource Latency 216
14.4.8 Semaphore Instructions 221
14.4.11 Thumb* Instructions 221
Compatibility: Intel 223
80200 Processor 223
A.3 Architecture Deviations 225
A.3.4 Write Buffer Behavior 226
A.3.5 External Aborts 226
A.3.6 Performance Differences 227
Optimization Guide B 229
B.2 Intel 230
80200 Processor Pipeline 230
F1 F2 ID RF X1 X2 231
M1 M2 Mx 231
B.2.1.5. Use of Bypassing 232
B.2.2.2. Pipeline Stalls 233
B.2.3 Main Execution Pipeline 234
Optimization Guide 235
B.2.4 Memory Pipeline 236
B.3 Basic Optimizations 237
B.3.1.2. Optimizing Branches 238
B.3.2 Bit Field Manipulation 241
B.4.1 Instruction Cache 245
• Interrupt handlers 246
• Real time clock handlers 246
• OS critical code 246
B.4.2 Data and Mini Cache 247
B.4.2.4. Creating On-chip RAM 248
B.4.2.5. Mini-data Cache 249
B.4.2.6. Data Alignment 250
B.4.2.7. Literal Pools 251
B.4.3 Cache Considerations 252
B.4.4 Prefetch Considerations 253
B.4.4.8. Cache Blocking 259
B.4.4.9. Prefetch Unrolling 259
B.4.4.10. Pointer Prefetch 260
B.4.4.11. Loop Interchange 261
B.4.4.12. Loop Fusion 261
B.5 Instruction Scheduling 263
B.6 Optimizing C Libraries 273
B.7 Optimizations for Size 273
Test Features C 275
Test Features 276
C.2.4.2. Bypass Register 280
C.2.5 TAP Controller 281
C.2.5.2. Run-Test/Idle State 282
C.2.5.3. Select-DR-Scan State 282
C.2.5.4. Capture-DR State 282
C.2.5.5. Shift-DR State 283
C.2.5.6. Exit1-DR State 283
C.2.5.7. Pause-DR State 283
C.2.5.8. Exit2-DR State 283
C.2.5.9. Update-DR State 284
C.2.5.11. Capture-IR State 284
C.2.5.12. Shift-IR State 284
C.2.5.13. Exit1-IR State 285
C.2.5.14. Pause-IR State 285
C.2.5.15. Exit2-IR State 285
C.2.5.16. Update-IR State 285

Comentarios a estos manuales

Sin comentarios

Intel Computer Hardware 80200 Manual de usuario Pagina 62

Comentarios a estos manuales

Relacionado con productos y manuales para Tarjetas de desarrollo Intel Computer Hardware 80200