Intel 8XC196Lx Manual de usuario

8XC196Lx Supplement to8XC196Kx, 8XC196Jx,87C196CA User’s ManualAugust 2004Order Number: 272973-003

11-1CHAPTER 11PROGRAMMING THE NONVOLATILE MEMORYThe 87C196LA and LB microcontrollers contain 24 Kbytes (2000–7FFFH) of one-time-pro-grammable read-onl

8XC196LX SUPPLEMENT11-211.3 SLAVE PROGRAMMING CIRCUIT AND ADDRESS MAPFigure 11-1 shows the circuit diagram and Table 11-3 details the address map for

11-3PROGRAMMING THE NONVOLATILE MEMORYFigure 11-1. Slave Programming CircuitTable 11-3. Slave Programming Mode Address MapDescription Address Comments

8XC196LX SUPPLEMENT11-411.4 SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAPFigure 11-2 shows the circuit and Table 11-4 details the address map for se

11-5PROGRAMMING THE NONVOLATILE MEMORYTable 11-4. Serial Port Programming Mode Address MapDescriptionAddress RangeNormal Operation Serial Port Program

ASignal Descriptions

A-1APPENDIX ASIGNAL DESCRIPTIONSThis appendix provides reference information for the pin functions of the 8XC196Lx microcon-trollers.A.1 FUNCTIONAL GR

1-1CHAPTER 1GUIDE TO THIS MANUALThis document is a supplement to the 8XC196Kx, 8XC196Jx, 87C196CA Microcontroller FamilyUser’s Manual. It describes th

8XC196LX SUPPLEMENTA-2Table A-1. 87C196LA Signals Arranged by Functional Categories Addr & Data Input/Output (Cont’d) Program Control Processor Co

A-3SIGNAL DESCRIPTIONSFigure A-1. 87C196LA 52-pin PLCC PackageP6.1 / EPA9 / COMP1P6.0 / EPA8 / COMP0P1.0 / EPA0 / T2CLKP1.1 / EPA1P1.2 / EPA2 / T2DIRP

8XC196LX SUPPLEMENTA-4Table A-2. 87C196LB Signals Arranged by Functional Categories Addr & Data Input/Output (Cont’d) Program Control Processor Co

A-5SIGNAL DESCRIPTIONSFigure A-2. 87C196LB 52-pin PLCC PackageP6.1 / EPA9 / COMP1P6.0 / EPA8 / COMP0P1.0 / EPA0 / T2CLKP1.1 / EPA1P1.2 / EPA2 / T2DIRP

8XC196LX SUPPLEMENTA-6Table A-3. 83C196LD Signals Arranged by Functional Categories Addr & Data Input/Output Input/Output (Cont’d) Processor Contr

A-7SIGNAL DESCRIPTIONSFigure A-3. 83C196LD 52-pin PLCC PackageA.2 DEFAULT CONDITIONSTable A-5 lists the values of the signals for the 87C196LA and 87C

8XC196LX SUPPLEMENTA-8Table A-5. 87C196LA, LB Default Signal Conditions PortSignalsAlternateFunctionsDuring RESET#ActiveUpon RESET#Inactive(Note 6)Idl

A-9SIGNAL DESCRIPTIONSTable A-6. 83C196LD Default Signal Conditions PortSignalsAlternateFunctionsDuring RESET#ActiveUpon RESET#Inactive(Note 6)IdlePow

Glossary

8XC196LX SUPPLEMENT1-2Appendix A — Signal Descriptions — provides reference information for the 8XC196Lx de-vice pins, including descriptions of the p

Glossary-1GLOSSARYThis glossary defines acronyms, abbreviations, and terms that have special meaning in this man-ual. (Chapter 1 discusses notational

8XC196LX SUPPLEMENTGlossary-2byte Any 8-bit unit of data.BYTE An unsigned, 8-bit variable with values from 0 through 28–1. CCBs Chip configuration byt

Glossary-3GLOSSARYcontention The detection of conflicting symbols or bits on the bus.crosstalk See off-isolation.DC input leakage Leakage current fro

8XC196LX SUPPLEMENTGlossary-4external address A 21-bit address is presented on the microcontroller’s pins. The address decoded by an external device d

Glossary-5GLOSSARYinternal address The 24-bit address that the microcontroller generates. See also external address.interrupt controller The module re

8XC196LX SUPPLEMENTGlossary-6maskable interrupts All interrupts except stack overflow, unimplemented opcode, and software trap. Maskable interrupts ca

Glossary-7GLOSSARYnonlinearity The maximum deviation of code transitions of the terminal-based characteristic from the corre-sponding code transitions

8XC196LX SUPPLEMENTGlossary-8prioritized interrupt NMI, stack overflow, or any maskable interrupt. Two of the nonmaskable interrupts (unimplemented op

Glossary-9GLOSSARYPTS vector A location in special-purpose memory that holds the starting address of a PTS control block.QUAD-WORD An unsigned, 64-bit

2Architectural Overview

8XC196LX SUPPLEMENTGlossary-10sample time uncertainty The variation in the sample time. sample window The period of time that begins when the sample c

Glossary-11GLOSSARYspecial-purpose memory A partition of memory used for storing the interrupt vectors, PTS vectors, chip configuration bytes, and sev

8XC196LX SUPPLEMENTGlossary-12VCC rejection The property of an A/D converter that causes it to ignore (reject) changes in VCC so that the actual chara

Index

Index-1INDEXAAddress map, 3-1Address partitionsmap, 3-1OTPROM, 11-1program memory, 11-1special-purpose memory, 11-1ALE, idle, powerdown, reset st

Index-2PPeriod (t), 2-4Port 0idle, powerdown, reset status, A-8, A-9overview, 5-1Port 1configuring, 5-3idle, powerdown, reset status, A-8, A-9ove

2-1CHAPTER 2ARCHITECTURAL OVERVIEWThis chapter describes architectural differences between the 8XC196Lx (87C196LA, 87C196LB,and 83C196LD) and the 8XC1

8XC196LX SUPPLEMENT2-22.2 BLOCK DIAGRAMFigure 2-1 is a simplified block diagram that shows the major blocks within the microcontroller.Observe that th

2-3ARCHITECTURAL OVERVIEWFigure 2-2. Clock Circuitry (87C196LA, LB Only)The rising edges of PH1 and PH2 generate the internal CLKOUT signal (Figure 2-

8XC196LX SUPPLEMENT2-4Figure 2-3. Internal Clock Phases (Assumes PLL is Bypassed)The combined period of phase 1 and phase 2 of the internal CLKOUT sig

2-5ARCHITECTURAL OVERVIEWFigure 2-4. Effect of Clock Mode on Internal CLKOUT Frequency2.4 EXTERNAL TIMINGYou can control the output frequency on the C

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellect

8XC196LX SUPPLEMENT2-6To program these bits, write the correct value to the locations shown in Table 2-4 using slave pro-gramming mode. During normal

2-7ARCHITECTURAL OVERVIEW2.5.1 I/O PortsThe I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, onthe 87C196LA and

3Address Space

3-1CHAPTER 3ADDRESS SPACEThis chapter describes the differences in the address space of the 8XC196Lx from that of the8XC196Kx.3.1 ADDRESS PARTITIONSTa

8XC196LX SUPPLEMENT3-23.2 REGISTER FILEFigure 3-1 compares the register file addresses of the 8XC196Lx and 8XC196Kx. The registerfile in Figure 3-1 is

3-3ADDRESS SPACEFigure 3-1. Register File Address MapTable 3-2. Register File Memory AddressesDevice and Hex Address RangeDescription Addressing Mode

8XC196LX SUPPLEMENT3-43.3 PERIPHERAL SPECIAL-FUNCTION REGISTERSTable 3-3 lists the peripheral SFR addresses. Highlighted addresses are unique to the 8

3-5ADDRESS SPACESIO and SSIO SFRs EPA SFRs (Continued)Address High (Odd) Byte Low (Even) Byte Address High (Odd) Byte Low (Even) Byte1FBEH Reserved Re

iiiCONTENTSCHAPTER 1GUIDE TO THIS MANUAL1.1 MANUAL CONTENTS...

8XC196LX SUPPLEMENT3-63.4 WINDOWINGWindowing maps a segment of higher memory (the upper register file or peripheral SFRs) intothe lower register file.

3-7ADDRESS SPACERegister RAM (87C196JV Only; Continued)1CE0H 67H33H19H1CC0H 66H1CA0H 65H32H1C80H 64H1C60H 63H31H18H1C40H 62H1C20H 61H30H1C00H 60HUpper

8XC196LX SUPPLEMENT3-8Upper Register File (CA, JR, JT, JV, KR, KT, LA, LB, LD)0160H 4BH25H12H0140H 4AH0120H 49H24H0100H 48HTable 3-4. Windows (Contin

4Standard and PTS Interrupts

4-1CHAPTER 4STANDARD AND PTS INTERRUPTSThe interrupt structure of the 8XC196Lx is the same as that of the 8XC196Jx. The only differenceis that the sla

8XC196LX SUPPLEMENT4-24.2 INTERRUPT REGISTERSThis section describes the changes in the interrupt register bit definitions for the 8XC196Lx fam-ily.Tab

4-3STANDARD AND PTS INTERRUPTS4.2.1 Interrupt Mask RegistersFigures 4-1 and 4-2 illustrate the interrupt mask registers for the 8XC196Lx microcontroll

8XC196LX SUPPLEMENT4-44.2.2 Interrupt Pending RegistersFigures 4-3 and 4-4 illustrate the interrupt pending registers for the 8XC196Lx microcontroller

4-5STANDARD AND PTS INTERRUPTSINT_PEND Address:Reset State:0009H00HWhen hardware detects an interrupt request, it sets the corresponding bit in the in

8XC196LX SUPPLEMENT ivCHAPTER 6SYNCHRONOUS SERIAL I/O PORT6.1 SSIO 0 CLOCK REGISTER...

8XC196LX SUPPLEMENT4-64.2.3 Peripheral Transaction Server RegistersFigures 4-5 and 4-6 illustrate the PTS interrupt select and service registers for t

4-7STANDARD AND PTS INTERRUPTSPTSSEL Address:Reset State:0004H0000HThe PTS select (PTSSEL) register selects either a PTS microcode routine or a standa

8XC196LX SUPPLEMENT4-8PTSSRV Address:Reset State:0006H0000HThe PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS in

5I/O Ports

5-1CHAPTER 5I/O PORTSThe I/O ports of the 8XC196Lx are functionally identical to those of the 8XC196Jx. However, onthe 87C196LA and LB, the reset stat

8XC196LX SUPPLEMENT5-2input signals set SFDIR. Even if a pin is to be used in special-function mode, you must still ini-tialize the pin as an input or

5-3I/O PORTSFigure 5-1. Ports 1, 2, 5, and 6 Internal Structure (87C196LA, LB Only)5.2.1 Configuring Ports 1, 2, 5, and 6 (Bidirectional Ports)Using t

8XC196LX SUPPLEMENT5-4impedance input, or open-drain output. The port direction and data output registers select the con-figuration for each pin. Comp

5-5I/O PORTSin using this pin. Be certain that your system meets the VIH specifications during reset to prevent inadvertent entry into ONCE mode or a

vCONTENTS8.6 PROGRAMMING THE J1850 CONTROLLER ... 8-168.6.1 Programming the J1850 Command (J_

8XC196LX SUPPLEMENT5-6Figure 5-2. Ports 3 and 4 Internal Structure (87C196LA, LB Only)Q2Q1Px_REGP34_DRVSampleLatchPH1 ClockInternal BusAddress/DataPx_

6Synchronous Serial I/O Port

6-1CHAPTER 6SYNCHRONOUS SERIAL I/O PORTThe synchronous serial I/O (SSIO) port on the 8XC196Lx has been enhanced, implementing twonew special function

8XC196LX SUPPLEMENT6-2For transmissions, SSIO0_CLK determines whether the SSIO shifts out data bits on rising or fall-ing clock edges. For receptions,

6-3SYNCHRONOUS SERIAL I/O PORTFor transmissions, SSIO1_CLK determines whether the SSIO shifts out data bits on rising or fall-ing clock edges. For rec

7Event Processor Array

7-1CHAPTER 7EVENT PROCESSOR ARRAYThe EPA on the 8XC196Lx is functionally identical to that of the 8XC196Jx; however, the8XC196Lx has only two capture/

8XC196LX SUPPLEMENTviFIGURESFigure Page2-1 8XC196Lx Block Diagram ...

8XC196LX SUPPLEMENT7-2Figure 7-1. EPA Block Diagram (87C196LA, LB Only)IndirectInterrupt ProcessorLogicEPAxInterruptA5269-01Timer-Counter UnitEPA9 / C

7-3EVENT PROCESSOR ARRAYFigure 7-2. EPA Block Diagram (83C196LD Only)IndirectInterrupt ProcessorLogicEPAxInterruptA5281-01TIMER1TIMER2Timer-Counter Un

8XC196LX SUPPLEMENT7-47.1.1 EPA Mask RegistersFigures 7-3 and 7-4 illustrate the EPA mask registers, EPA_MASK and EPA_MASK1, for the8XC196Lx microcont

7-5EVENT PROCESSOR ARRAY7.1.2 EPA Pending RegistersFigures 7-5 and 7-6 illustrate the EPA pending registers, EPA_PEND and EPA_PEND1, for the8XC196Lx m

8XC196LX SUPPLEMENT7-67.1.3 EPA Interrupt Priority Vector RegisterFigure 7-7 illustrates the EPA interrupt priority vector (EPAIPV) register for the 8

8J1850 Communications Controller

8-1CHAPTER 8J1850 COMMUNICATIONS CONTROLLERThe J1850 communications controller manages communications between multiple networknodes. This integrated p

8XC196LX SUPPLEMENT8-2The J1850 controller can handle network protocol functions including message frame sequenc-ing, bit arbitration, in-frame respon

8-3J1850 COMMUNICATIONS CONTROLLER8.2 J1850 CONTROLLER SIGNALS AND REGISTERSTable 8-1 describes the J1850 controller’s pins, and Table 8-2 describes t

viiCONTENTSFIGURESFigure Page11-1 Slave Programming Circuit...11

8XC196LX SUPPLEMENT8-48.3 J1850 CONTROLLER OPERATIONThis section describes the control state machine (which contains the cyclic redundancy checkgenera

8-5J1850 COMMUNICATIONS CONTROLLER8.3.1.2 Bus ContentionBus contention arises when multiple nodes attempt to access and transmit message frames across

8XC196LX SUPPLEMENT8-68.3.2.1 Clock PrescalerBecause the 87C196LB microcontroller can operate at a variety of input frequencies (FXTAL1), theclock pre

8-7J1850 COMMUNICATIONS CONTROLLERFigure 8-3. Huntzicker Symbol Definition for J1850A symbol is defined as a timing-level formatted bit. The VPW symbo

8XC196LX SUPPLEMENT8-8of arbitration, nodes A, C, and D are all transmitting an “active 0” symbol, thus the idle state ofthe “passive 1” symbol is ove

8-9J1850 COMMUNICATIONS CONTROLLERFigure 8-6. J1850 Message FramesA standard message frame is initiated by the responder and contains no more than 11

8XC196LX SUPPLEMENT8-10(J_CFG.7) and considers whether the IFR message response has a CRC byte appended. Figure8-7 depicts the SAE preferred, active-l

8-11J1850 COMMUNICATIONS CONTROLLERFigure 8-8. Definition for Start and End of Frame SymbolsTable 8-4 details the symbol timing characteristics suppor

8XC196LX SUPPLEMENT8-128.4.2 In-frame Response MessagingThere are three types of in-frame response (IFR) message framings: type 1 (a single byte from

8-13J1850 COMMUNICATIONS CONTROLLERFigure 8-10. IFR Type 2 Message Frame8.4.2.3 IFR Messaging Type 3: Multiple Bytes, Single ResponderIFR messaging ty

8XC196LX SUPPLEMENTviiiTABLESTable Page1-1 Related Documents...

8XC196LX SUPPLEMENT8-14Transmitting the message requires that you first program the J1850 command (J_CMD) registerto specify the number of bytes you w

8-15J1850 COMMUNICATIONS CONTROLLERNOTEAn overrun condition can occur on transmission if the transmit buffer, JTX_BUF, is overwritten.8.5.2 Receiving

8XC196LX SUPPLEMENT8-16If a third byte is received before J_RX is read, a J1850ST core interrupt is generated and theOVR_UNDR (J_STAT.3) bit records a

8-17J1850 COMMUNICATIONS CONTROLLERJ_CMDAddress:Reset State:1F51H00HThe J1850 command (J_CMD) register determines the messaging type, specifies the nu

8XC196LX SUPPLEMENT8-188.6.2 Programming the J1850 Configuration (J_CFG) RegisterThe J1850 configuration register (Figure 8-17) selects the proper osc

8-19J1850 COMMUNICATIONS CONTROLLER8.6.3 Programming the J1850 Delay Compensation (J_DLY) RegisterThe J1850 delay compensation register (Figure 8-18)

8XC196LX SUPPLEMENT8-20J_DLYAddress:Reset State:1F58H00HThe J1850 delay (J_DLY) register allows you compensate for the inherent propagation delays and

8-21J1850 COMMUNICATIONS CONTROLLER8.6.4 Programming the J1850 Status (J_STAT) RegisterThe J1850 status register (Figure 8-19) provides the current st

8XC196LX SUPPLEMENT8-222 MSG_TX Message Transmit InterruptThis bit signals the successful transmission of a message upon detecting the EOD symbol.0 =

9Minimum Hardware Considerations

1Guide to This Manual

9-1CHAPTER 9MINIMUM HARDWARE CONSIDERATIONSThis chapter discusses the major hardware consideration differences between the 8XC196Lx andthe 8XC196Kx. T

8XC196LX SUPPLEMENT9-29.2 DESIGN CONSIDERATIONS FOR 8XC196LA, LB, AND LD With the exception of a few new multiplexed functions, the 8XC196Lx microcont

10Special Operating Modes

10-1CHAPTER 10SPECIAL OPERATING MODESThe 8XC196Lx’s idle and powerdown modes are the same as those of the 8XC196Kx. However,the clock circuitry has ch

8XC196LX SUPPLEMENT10-2Figure 10-1. Clock Circuitry (87C196LA, LB Only)10.2 ENTERING AND EXITING ONCE MODEONCE mode isolates the device from other com

10-3SPECIAL OPERATING MODESan output. If you choose to configure this pin as an input, always hold it low during reset and en-sure that your system me

11Programming the Nonvolatile Memory