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Datasheet 13
Introduction
1.6 Reference Documents
The reader of this specification should also be familiar with material and concepts presented in the
following documents:
Note: Contact your Intel representative or check http://developer.intel.com for the latest revision of the
reference documents.
Title Document Number
Intel
®
Itanium
®
2 Processor Specification Update 251141
Intel
®
Itanium
®
Architecture Software Developer’s Manual, Volume 1:
Application Architecture
245317
Intel
®
Itanium
®
Architecture Software Developer’s Manual, Volume 2: System
Architecture
245318
Intel
®
Itanium
®
Architecture Software Developer’s Manual,
Volume 3: Instruction Set Reference
245319
Intel
®
Itanium
®
2 Processor Reference Manual for Software Development and
Optimization
251110
Intel
®
Itanium
®
Processor Family System Abstraction Layer Specification 245359
ITP700 Debug Port Design Guide 249679
System Management Bus Specification http://www.smbus.org/specs
- 2 Processor 1
- 2 Datasheet 2
- Contents 3
- 4 Datasheet 4
- Datasheet 5 5
- 6 Datasheet 6
- Datasheet 7 7
- Revision History 8
- 10 Datasheet 10
- 1 Introduction 11
- Cache Sizes 12
- 1.4 Terminology 12
- 1.5 State of Data 12
- 1.6 Reference Documents 13
- Introduction 14
- 2 Electrical Specifications 15
- 2.2.2 Signal Descriptions 16
- 2.3 Package Specifications 17
- 2.4 Signal Specifications 18
- Electrical Specifications 19
- 20 Datasheet 20
- 2.4.1 Maximum Ratings 22
- Measurement Guidelines 23
- 2.5.3 Activity Factor 24
- Specifications 25
- 26 Datasheet 26
- Datasheet 27 27
- 2.5.6 Wired-OR Signals 28
- Datasheet 29 29
- 30 Datasheet 30
- Datasheet 31 31
- 2.7 Itanium 32
- Processor Clocking 32
- Datasheet 33 33
- 34 Datasheet 34
- Datasheet 35 35
- 1. L = GND, H = V 36
- 3 Pinout Specifications 37
- Pinout Specifications 38
- 4 Mechanical Specifications 69
- 70 Datasheet 70
- Datasheet 71 71
- 4.2 Package Marking 72
- Datasheet 73 73
- Mechanical Specifications 74
- 5 Thermal Specifications 75
- 5.2 Case Temperature 76
- Datasheet 77 77
- Thermal Specifications 78
- 6 System Management Feature 79
- 80 Datasheet 80
- 6.1.3 SMBus Device Addressing 81
- 6.2 Processor Information ROM 82
- Datasheet 83 83
- 84 Datasheet 84
- 6.3 Scratch EEPROM 85
- Supported SMBus Transactions 85
- 6.5 Thermal Sensing Device 86
- Transactions 87
- 88 Datasheet 88
- 6.7.2 Thermal Limit Registers 89
- 6.7.3 Status Register 89
- 6.7.4 Configuration Register 89
- 90 Datasheet 90
- A Signals Reference 91
- A.1.6 ATTR[3:0]# (I/O) 92
- A.1.7 BCLKp/BCLKn (I) 92
- A.1.8 BE[7:0]# (I/O) 92
- A.1.9 BERR# (I/O) 93
- A.1.10 BINIT# (I/O) 94
- A.1.11 BNR# (I/O) 94
- A.1.12 BPM[5:0]# (I/O) 94
- A.1.13 BPRI# (I) 94
- A.1.15 BREQ[3:0]# (I/O) 95
- 96 Datasheet 96
- A.1.22 DBSY_C2# (O) 97
- A.1.23 DEFER# (I) 97
- A.1.24 DEN# (I/O) 97
- A.1.25 DEP[15:0]# (I/O) 97
- A.1.26 DHIT# (I) 97
- 98 Datasheet 98
- Datasheet 99 99
- A.1.39 IGNNE# (I) 100
- A.1.40 INIT# (I) 100
- A.1.41 INT (I) 100
- A.1.42 IP[1:0]# (I) 100
- A.1.43 LEN[2:0]# (I/O) 100
- Datasheet 101 101
- A.1.52 RP# (I/O) 102
- A.1.51 RESET# (I) 102
- Datasheet 103 103
- A.1.60 TCK (I) 104
- A.1.61 TDI (I) 104
- A.1.62 TDO (O) 104
- A.1.63 THRMTRIP# (O) 104
- A.2 Signal Summaries 105
- 106 Datasheet 106
- Datasheet 107 107
- Signals Reference 108
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