Intel 80526KZ800256 Ficha de datos

PENTIUM® III XEON™ PROCESSOR AT 700 MHz and 900 MHz. Datasheet Product Features  Binary compatible with a

ELECTRICAL SPECIFICATIONS 9 3. ELECTRICAL SPECIFICATIONS 3.1 System Bus and VREF The Pentium® III Xeon™ processor signals use a variation of the

APPENDIX 99 10.1.47 SELFSB0 (I) SELFSB1 (O) The Pentium® III Xeon™ processor at 700 MHz and 900 MHz adds a definition to the SELFSB [1:0] pins wh

APPENDIX 100 Table 59. Description of SELFSB pins processor Pin Location Pin Name Functionality A7 SELFSB1 Output, Frequency Detect Pentium®

APPENDIX 101 The SMBCLK (SMBus Clock) signal is an input clock to the system management logic which is required for operation of the system manag

APPENDIX 102 10.1.60 TRDY# (I) The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready to receive a write or impl

APPENDIX 103 Table 61. Input Signals Name Active Level Clock Signal Group Qualified A20M# Low Asynch CMOS Input Always BPRI# Low BCLK A

APPENDIX 104 Table 62. I/O Signals (Single Driver) Name Active Level Clock Signal Group Qualified SELFSB1 TBD TBD TBD TBD BR0# Low BCLK AG

ELECTRICAL SPECIFICATIONS 10 For a summary of the power and ground pins listed above, see Table 50 and Table 51 in section 7.3 of this document f

ELECTRICAL SPECIFICATIONS 11 3.3 Decoupling Guidelines Due to the large number of transistors and high internal clock speeds, the processor is

ELECTRICAL SPECIFICATIONS 12 Table 1 System Bus-to-Core Frequency Ratio Configuration1 Ratio of BCLK to Core Frequency 100 MHz Target Frequency

ELECTRICAL SPECIFICATIONS 13 A20M#IGNNE#LINT1/NMILINT0/INTRProcessors1KΩ2.5 VSet Ratio:CRESET#2Mux2.5 V1-4 000809 Figure 2. Logical1 Schematic f

ELECTRICAL SPECIFICATIONS 14 VID_CORE[4:0] controls the voltage supply to the processor core and VID_L2[4:0] controls the voltage supply to the

ELECTRICAL SPECIFICATIONS 15 Table 2. FMB Core and L2 Voltage Identification Definition 1, 2 Processor pins VID4 VID3 VID2 VID1 VID0 Vcc Core3 L2

ELECTRICAL SPECIFICATIONS 16 pull-ups. A resistor of greater than or equal to 10KΩ may be used to connect the VID signals to the converter input.

ELECTRICAL SPECIFICATIONS 17 Table 3. Processor pin Groups Group Name Signals AGTL+ Input BPRI#, BR[3:1]#1, DEFER#, RESET#, RS[2:0]#, RSP#, TR

ELECTRICAL SPECIFICATIONS 18 A Debug Port is described in Chapter 8. The Debug Port must be placed at the start and end of the TAP chain with TDI

ii Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any in

ELECTRICAL SPECIFICATIONS 19 NOTE Unless otherwise noted, each specification applies to all Pentium® III Xeon™ processor at 700 MHz and 900 MHz.

ELECTRICAL SPECIFICATIONS 20 Table 6. Current Specifications 1,10 Symbol Parameter Min Typ Max Unit Notes Icc_core @ 2.74V VCC_CORE 700 MH

ELECTRICAL SPECIFICATIONS 21 8. VCC_SMB must be connected to 3.3V power supply (even if the SMBus features are not used) in order for the proces

ELECTRICAL SPECIFICATIONS 22 6. Maximum VIL at the processor core pin is specified as 2/3 VTT – 0.2V. 7. Minimum VIH at the processor core pin is

ELECTRICAL SPECIFICATIONS 23 Table 11 Internal Parameters for the AGTL+ Bus Symbol Parameter Min Typ Max Units Notes RTT Termination Resistor

ELECTRICAL SPECIFICATIONS 24 3.12 System Bus AC Specifications The system bus timings specified in this section are defined at the processor

ELECTRICAL SPECIFICATIONS 25 Table 12. System Bus AC Specifications (Clock) at the processor Core Pins 1, 2, 3 T# Parameter Min Nom Max Unit

ELECTRICAL SPECIFICATIONS 26 Table 14. AGTL+ Signal Group, System Bus AC Specifications at the Core Pins1 RL = 25 ohms Terminated to 1.5V T# Para

ELECTRICAL SPECIFICATIONS 27 Table 16. System Bus AC Specifications (Reset Conditions1) T# Parameter Min Max Unit Figure Notes T16: Reset C

ELECTRICAL SPECIFICATIONS 28 Table 18. System Bus AC Specifications (TAP Connection) at the processor Core 1 T# Parameter Min Max Unit Figu

TABLE OF CONTENTS 2 TABLE OF CONTENTS PRODUCT FEATURES...

ELECTRICAL SPECIFICATIONS 29 Table 19. SMBus Signal Group, AC Specifications at the Edge Fingers T# Parameter Min Max Unit Figure Notes T50:

ELECTRICAL SPECIFICATIONS 30 SCLK2.46V0.84VThTlTrTfTrT54TfT55T52ThT53Tl====2.97V0.84V SMBUSCLK Figure 4. SMBCLK Clock Waveform ClockSignalTxTxT

ELECTRICAL SPECIFICATIONS 31 BCLKRESET#Configuration(A20M#, IGNNE#,LINT[1:0])Configuration(A[14:5]#, BR0#,FLUSH#, INIT#)P6CB 764TtT9 (GTL+ Inp

ELECTRICAL SPECIFICATIONS 32 TCKTDI, TMSInputSignalsTDOOutputSignals6C 661.25VTvTwTrTsTxTuTyTz1.25VTrT43 (All Non-Test Inputs Setup Time)=TsT44 (

SIGNAL QUALITY 33 4. Signal Quality Signals driven on the system bus should meet signal quality specifications to ensure that the components rea

SIGNAL QUALITY 34 4.2 AGTL+ Signal Quality Specifications Refer to the Pentium II Processor Developer's Manual (Order Number 243341) for t

SIGNAL QUALITY 35 Overshoot/Undershoot is the absolute value of the maximum voltage differential across the input buffer relative to the termina

SIGNAL QUALITY 36 The overshoot/undershoot specifications listed in the following tables specify the allowable overshoot/undershoot for a single

SIGNAL QUALITY 37 1. Unless otherwise noted, all guidelines in this table apply to all processor frequencies. 2. Overshoot Magnitude and Unders

SIGNAL QUALITY 38 pads. Overshoot/Undershoot shown in Figure 14 is for illustrative purposes only to help explain Ringback and Settling Limit. R

TABLE OF CONTENTS 3 5.1.3 STOP-GRANT STATE — STATE 3... 42 5.1.4 HALT/GRA

SIGNAL QUALITY 39 1. Activity Factor based on period equal to 30 nS. 2. Overshoot/Undershoot Magnitude = 2.3V is an Absolute value and should

SIGNAL QUALITY 40 4.3.4 2.5V TOLERANT BUFFER RINGBACK SPECIFICATION The ringback specification is the voltage at a receiving pin that a signal r

PROCESSOR FEATURES 41 5. PROCESSOR FEATURES 5.1 Low Power States and Clock Control The processor allows the use of Auto HALT, Stop-Grant, and Sl

PROCESSOR FEATURES 42 2. Auto HALT Power Down StateBCLK running.Snoops and interrupts allowed.HA L T Instruction andHALT Bus Cycle GeneratedINIT

PROCESSOR FEATURES 43 5.1.5 SLEEP STATE — STATE 5 The Sleep state is a very low power state in which the processor maintains its context, mai

PROCESSOR FEATURES 44 R10K1/16W5%R 10K 1/16W 5% R 10K 1/16W 5% R 10K 1/16W 5% R 10K 1/16W 5% SDA SCL WP SA1 Core A2DVccSCSDA1A0StbyCAALERT#SMBAL

PROCESSOR FEATURES 45 Systems implementing analog sensing should read the PIROM first, then compare that value with the measured VIN_SENSE rath

PROCESSOR FEATURES 46 Table 31. Processor Information ROM Format Offset/Section # of Bits Function Notes HEADER: 00h 8 Data Format Revision

PROCESSOR FEATURES 47 16 L2 Cache Size 16-Bit binary number (in Kbytes) 8 Reserved 16 OCVR Output Voltage ID1 Voltage in mV 8 OCVR Out

PROCESSOR FEATURES 48 5.2.2 SCRATCH EEPROM Also available on the SMBus is an EEPROM that may be used for other data at the system or processor

TABLE OF CONTENTS 4 10.1 ALPHABETICAL SIGNALS REFERENCE ... 90

PROCESSOR FEATURES 49 Table 33. Receive Byte SMBus Packet S Device Address R/W* A* Data A* P 1 7 bits 1 0 8 bits 1 1 Table 33 diagrams the

PROCESSOR FEATURES 50 uniquely determined for each unit. The procedure causes each unit to dissipate its maximum power (which can vary from unit

PROCESSOR FEATURES 51 1. This is an 8-bit field. The device that sent the alert will respond to the ARA Packet with its address in the seven mos

PROCESSOR FEATURES 52 5.2.6.3 Status Register The status register shown in Table 42 indicates which (if any) thermal value thresholds have been

PROCESSOR FEATURES 53 03h 0.5 04h 1 05h 2 06h 4 07h 8 08h to FFh Reserved for future use 5.2.7 SMBus Device Addressing Of the addresses broadc

PROCESSOR FEATURES 54 Table 45. Thermal Sensor SMBus Addressing Address (Hex) Upper Address1 Slot Select 8-bit Address Word on Serial Bus

THERMAL SPECIFICATIONS 55 6. THERMAL SPECIFICATIONS AND DESIGN CONSIDERATIONS The processor contains a thermal plate for heatsink attachment. Th

THERMAL SPECIFICATIONS 56 Table 47 Power Estimates 1 Frequency Core Power2 (W) 2.8V OCVR Power (W) 5V/12V OCVR Power (W) 2.8V Cartridge Po

THERMAL SPECIFICATIONS 57 6.1.2 PLATE FLATNESS SPECIFICATION The thermal plate flatness for the processor is specified to 0.010” across the ent

THERMAL SPECIFICATIONS 58 the design of the heatsink and airflow around the heatsink. General Information on thermal interfaces and heatsink desi

TABLE OF CONTENTS 5 10.1.55 TDI (I) ...

THERMAL SPECIFICATIONS 59 To ensure functional and reliable processor operation, the processor's thermal plate temperature (TPLATE) must be

MECHANICAL SPECIFICATIONS 60 7. MECHANICAL SPECIFICATIONS The processor use S.E.C. cartridge package technology. The S.E.C. cartridge contains t

MECHANICAL SPECIFICATIONS 61 Figure 23. S.E.C. Cartridge Cooling Solution Attach Details (Notes follow)

MECHANICAL SPECIFICATIONS 62 Figure 24. S.E.C. Cartridge Retention Enabling Details (Notes follow)

MECHANICAL SPECIFICATIONS 63 Figure 25. SEC Cartridge Retention Enabling Details 1. Maximum protrusions of the mechanical heatsink attach medi

MECHANICAL SPECIFICATIONS 64 7.1 Weight The maximum weight of a processor and thermal solution is approximately 500 grams. 7.2 Cartridge to Conn

MECHANICAL SPECIFICATIONS 65 Figure 28. Front View of Connector Mating Details NOTES: Retention devices for this cartridge must accommodate thi

MECHANICAL SPECIFICATIONS 66 7.3 Substrate Edge Finger Signal Listing Table 50 is the processor substrate edge finger listing in order by p

MECHANICAL SPECIFICATIONS 67 Table 50. Signal Listing in Order by Pin Number Pin No. Pin Name Signal Buffer Type Pin No. Pin Name Signal Buff

MECHANICAL SPECIFICATIONS 68 Table 50. Signal Listing in Order by Pin Number Pin No. Pin Name Signal Buffer Type Pin No. Pin Name Signal Buff

INTRODUCTION 6 1. INTRODUCTION The Pentium® III Xeon™ processor at 700 MHz and 900 MHz, like the Pentium® Pro, Pentium® II, Pentium® II Xeon™ and

MECHANICAL SPECIFICATIONS 69 Table 50. Signal Listing in Order by Pin Number Pin No. Pin Name Signal Buffer Type Pin No. Pin Name Signal Buff

MECHANICAL SPECIFICATIONS 70 Table 51. Signal Listing in Order by Pin Name Pin No. Pin Name Signal Buffer Type B124 A#[03] AGTL+ I/O A124 A#

MECHANICAL SPECIFICATIONS 71 Pin No. Pin Name Signal Buffer Type B93 D#[04] AGTL+ I/O A92 D#[05] AGTL+ I/O B92 D#[06] AGTL+ I/O B90 D#[07]

MECHANICAL SPECIFICATIONS 72 Pin No. Pin Name Signal Buffer Type A138 DBSY# AGTL+ I/O A132 DEFER# AGTL+ Input A36 DEP#[0] AGTL+ I/O A38 DEP#[1

MECHANICAL SPECIFICATIONS 73 Pin No. Pin Name Signal Buffer Type A159 SA2 SMBus Input A9 SELFSB0 CMOS Input A7 SELFSB1 CMOS Output B18 SLP# C

MECHANICAL SPECIFICATIONS 74 Pin No. Pin Name Signal Buffer Type B112 VCC_L2 (N/C) L2 Cache Vcc B115 VCC_L2 (N/C) L2 Cache Vcc B118 VCC_L2 (N/C

MECHANICAL SPECIFICATIONS 75 Pin No. Pin Name Signal Buffer Type A28 VSS Ground A31 VSS Ground A34 VSS Ground A37 VSS Ground A4 VSS Ground

INTEGRATION TOOLS 76 8. INTEGRATION TOOLS The integration tool set for system designs will include an In-Target Probe (ITP) for program executio

INTEGRATION TOOLS 77 The ITP will connect to the system through the debug port. Recommended connectors, to mate the ITP cable with the debug port

INTEGRATION TOOLS 78 Name Pin Description Specification Requirement Notes RESET# 1 Reset signal from MP cluster to ITP. Terminate2 signal pr

TERMINOLOGY 7 2. TERMINOLOGY In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a signal is in th

INTEGRATION TOOLS 79 Table 52. Debug Port Pinout Description and Requirements1 Name Pin Description Specification Requirement Notes BSEN# 14

INTEGRATION TOOLS 80 NOTES: 1. Resistor values with “~” preceding them can vary from the specified value; use resistor as close as possible to

INTEGRATION TOOLS 81 The TDO signal of each processor has a 2.5V Tolerant open-drain driver. The TDI signal of each processor contains a 150Ω pul

INTEGRATION TOOLS 82 NOTE The buffer rise and fall edge rates should NOT be FASTER than 3nS. Edge rates faster than this in the system can con

BOXED PROCESSOR SPECIFICATIONS 83 9. BOXED PROCESSOR SPECIFICATIONS 9.1 Introduction The Pentium® III Xeon™ processor at 700 MHz and 900 MHz is

BOXED PROCESSOR SPECIFICATIONS 84 BDAC Figure 34. Side View Space Requirements for the Boxed Processor

BOXED PROCESSOR SPECIFICATIONS 85 EF Figure 35. Front View Space Requirements for the Boxed Processor 9.2.1 BOXED PROCESSOR HEATSINK DIMENSIONS

BOXED PROCESSOR SPECIFICATIONS 86 processor does not require additional heatsink supports. Heatsink supports are not shipped with the boxed pro

BOXED PROCESSOR SPECIFICATIONS 87 Figure 36. Boxed Processor Heatsink Performance Figure 36 also shows the performance of the boxed processor

BOXED PROCESSOR SPECIFICATIONS 88 1.54.24 Figure 38. Side View Space Recommendation for the Auxiliary Fan Figure 39. Front View Space Reco

TERMINOLOGY 8 Additional terms referred to in this and other related documentation: • SC330.1 — An enhanced electrical and mechanical interface b

BOXED PROCESSOR SPECIFICATIONS 89 processor does not ship with an auxiliary fan, it is highly recommended that a power header be provided. It is

APPENDIX 90 10. APPENDIX This appendix provides an alphabetical listing of all Pentium® III Xeon™ processor at 700 MHz and 900 MHz signals and

APPENDIX 91 The BCLK (Bus Clock) is a 2.5V tolerant signal that determines the bus frequency. All processor system bus agents must receive this s

APPENDIX 92 The BR[3:1]# (Bus Request) pins drive the BREQ[3:0]# signals on the system. The BR[3:0]# pins are interconnected in a rotating manner

APPENDIX 93 10.1.17 DBSY# (I/O) The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving data on the system bus to indi

APPENDIX 94 an external error signal (e.g. NMI) by system core logic. The processor will keep IERR# asserted until it is handled in software, or

APPENDIX 95 10.1.31 L2_SENSE On Pentium® III Xeon™ processor at 500 MHz and 550 MHz cartridges, L2_SENSE is routed from the edge of the connec

APPENDIX 96 specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time t

APPENDIX 97 Figure 42. PWRGD Implementation 10.1.41 REQ[4:0]# (I/O) The REQ[4:0]# (Request Command) signals must connect the

APPENDIX 98 10.1.42 RESET# (I) Asserting the RESET# signal resets all processors to known states and invalidates their L1 and L2 caches without