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Processor Configuration Registers
64 Datasheet, Volume 2
2.7.26 SMICMD—SMI Command Register
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively. Note that one and only one message type can be enabled.
2.7.27 SKPD—Scratchpad Data Register
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
B/D/F/Type: 0/0/0/PCI
Address Offset: CC–CDh
Reset Value: 0000h
Access: RO, RW
Bit Attr
Reset
Value
Description
15:12 RO 0h Reserved
11 RW 0b
SMI on Processor Thermal Sensor Trip (TSTSMI)
1 = A SMI DMI special cycle is generated by the processor when the thermal
sensor trip requires an SMI. A thermal sensor trip point cannot generate
more than one special cycle.
0 = Reporting of this condition using SMI messaging is disabled.
10:2 RO 000h Reserved
1RW 0bReserved
0RW 0bReserved
B/D/F/Type: 0/0/0/PCI
Address Offset: DC–DFh
Reset Value: 0000_0000h
Access: RW
Bit Attr
Reset
Value
Description
31:0 RW
0000_000
0h
Scratchpad Data (SKPD)
1 DWORD of data storage.
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