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Datasheet 13
Low Power Features
2.1.1.3 C1/MWAIT Powerdown State
C1/MWAIT is a low-power state entered when the processor core executes the MWAIT
instruction. Processor behavior in the C1/MWAIT state is identical to the C1/AutoHALT
state except that there is an additional event that can cause the processor core to
return to the C0 state: the Monitor event. See the Intel® 64 and IA-32 Intel®
Architecture Software Developer's Manual, Volume 2A/2B: Instruction Set Reference
for more information.
2.1.1.4 Core C2 State
The core of the processor can enter the C2 state by initiating a P_LVL2 I/O read to the
P_BLK or an MWAIT(C2) instruction, but the processor does not issue a Stop Grant
Acknowledge special bus cycle unless the STPCLK# pin is also asserted.
The processor in C2 state processes only the bus snoops. The processor enters a
snoopable sub-state (not shown in Figure 2) to process the snoop and then return to
the C2 state.
2.1.1.5 Core C3 State
Core C3 state is a very low-power state the processor core can enter while maintaining
context. The core of the processor can enter the C3 state by initiating a P_LVL3 I/O
read to the P_BLK or an MWAIT(C3) instruction. Before entering the C3 state, the
processor core flushes the contents of its L1 cache into the processor’s L2 cache.
Except for the caches, the processor core maintains all its architectural state in the C3
state. The Monitor remains armed if it is configured. All of the clocks in the processor
core are stopped in the C3 state.
Because the core’s caches are flushed, the processor keeps the core in the C3 state
when the processor detects a snoop on the FSB. The processor core transitions to the
C0 state upon the occurrence of a Monitor event, SMI#, INIT#, LINT[1:0] (NMI, INTR),
or FSB interrupt message. RESET# causes the processor core to immediately initialize
itself.
2.1.1.6 Core C4 State
Individual cores of the dual-core processor that have C4 can enter the C4 state by
initiating a P_LVL4 I/O read to the P_BLK or an MWAIT(C4) instruction. The processor
core behavior in the C4 state is nearly identical to the behavior in the C3 state. The
only difference is that if both processor cores are in C4, the central power management
logic will request that the entire processor enter the Deeper Sleep package low-power
state (see Section 2.1.2.6)
2.1.2 Package Low-Power States
Package level low-power states are applicable to the processor.
2.1.2.1 Normal State
This is the normal operating state for the processor. The processor enters the Normal
state when the core is in the C0, C1/AutoHALT, or C1/MWAIT state.
2.1.2.2 Stop-Grant State
When the STPCLK# pin is asserted the core of the processor enters the Stop-Grant
state within 20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle. When the STPCLK# pin is deasserted the core returns
to the previous core low-power state.
- Dual-Core on 45-nm Process 1
- 2 Datasheet 2
- Contents 3
- 4 Datasheet 4
- Revision History 5
- 6 Datasheet 6
- 1 Introduction 7
- 1.1 Terminology 8
- 1.2 References 9
- Introduction 10
- 10 Datasheet 10
- 2 Low Power Features 11
- 2.1.1 Core Low-Power States 12
- Datasheet 13 13
- Low Power Features 13
- 2.1.2.4 Sleep State 14
- 2.1.2.6 Deeper Sleep State 15
- 2.1.2.5 Deep Sleep State 15
- 2.3 Low-Power FSB Features 16
- Datasheet 17 17
- 18 Datasheet 18
- 3 Electrical Specifications 19
- 3.5 Reserved and Unused Pins 22
- 3.7 FSB Signal Groups 23
- Table 4. FSB Pin Groups 24
- 3.8 CMOS Signals 25
- 3.9 Maximum Ratings 25
- Electrical Specifications 26
- 26 Datasheet 26
- Processors 28
- 4 Package Mechanical 33
- Specifications and Pin 33
- Information 33
- 34 Datasheet 34
- Datasheet 35 35
- 36 Datasheet 36
- Datasheet 37 37
- 38 Datasheet 38
- (Sheet 1 of 2) 39
- (Sheet 2 of 2) 40
- Datasheet 41 41
- 42 Datasheet 42
- Datasheet 43 43
- 44 Datasheet 44
- (Sheet 1 of 16) 45
- (Sheet 2 of 16) 45
- (Sheet 3 of 16) 46
- (Sheet 4 of 16) 46
- (Sheet 5 of 16) 47
- (Sheet 6 of 16) 47
- (Sheet 7 of 16) 48
- (Sheet 8 of 16) 48
- (Sheet 9 of 16) 49
- (Sheet 10 of 16) 49
- (Sheet 11 of 16) 50
- (Sheet 12 of 16) 50
- (Sheet 13 of 16) 51
- (Sheet 14 of 16) 51
- (Sheet 2 of 17) 53
- (Sheet 3 of 17) 53
- (Sheet 4 of 17) 54
- (Sheet 5 of 17) 54
- (Sheet 6 of 17) 55
- (Sheet 7 of 17) 55
- (Sheet 8 of 17) 56
- (Sheet 9 of 17) 56
- (Sheet 10 of 17) 57
- (Sheet 11 of 17) 57
- (Sheet 12 of 17) 58
- (Sheet 13 of 17) 58
- (Sheet 14 of 17) 59
- (Sheet 15 of 17) 59
- (Sheet 16 of 17) 60
- (Sheet 17 of 17) 60
- 74 Datasheet 74
- together with V 81
- 82 Datasheet 82
- 5 Thermal Specifications and 83
- Design Considerations 83
- 5.1.1 Thermal Diode 85
- 5.1.2 Thermal Diode Offset 87
- 5.1.3 Intel® Thermal Monitor 88
- 5.1.4 Digital Thermal Sensor 89
- 5.1.6 PROCHOT# Signal Pin 90
- Datasheet 91 91
- 92 Datasheet 92
- Datasheet 1 93
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