Intel Core 2 Quad Q6700 Ficha de datos

Document Number: 315592-005Intel® Core™2 Extreme Quad-Core Processor QX6000Δ Sequence and Intel® Core™2 Quad Processor Q6000Δ SequenceDatasheet—on 65

Introduction10 Datasheet“Front Side Bus” refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB

Datasheet 11Introduction• Enhanced Intel Technology SpeedStep® Technology — Enhanced Intel Technology SpeedStep® Technology allows trade-offs to be ma

Introduction12 Datasheet

Datasheet 13Electrical Specifications2 Electrical SpecificationsThis chapter describes the electrical characteristics of the processor interfaces and

Electrical Specifications14 Datasheet2.2.3 FSB DecouplingThe processor integrates signal termination on the die. In addition, some of the high frequen

Datasheet 15Electrical SpecificationsTable 2. Voltage Identification DefinitionVID6 VID5 VID4 VID3 VID2 VID1 VCC_MAXVID6 VID5 VID4 VID3 VID2 VID1 VCC_

Electrical Specifications16 Datasheet2.4 Reserved, Unused, and TESTHI SignalsAll RESERVED lands must remain unconnected. Connection of these lands to

Datasheet 17Electrical Specifications2.5 Voltage and Current Specification2.5.1 Absolute Maximum and Minimum RatingsTable 3 specifies absolute maximum

Electrical Specifications18 Datasheet2.5.2 DC Voltage and Current SpecificationTable 4. Voltage and Current SpecificationsSymbol Parameter Min Typ Max

Datasheet 19Electrical Specifications8.ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1 for details.9. These Processors have

2 DatasheetINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO AN

Electrical Specifications20 DatasheetNOTES:1. The loadline specification includes both static and transient limits except for overshoot allowed as sho

Datasheet 21Electrical Specifications2.5.3 VCC OvershootThe processor can tolerate short transient overshoot events where VCC exceeds the VID voltage

Electrical Specifications22 Datasheet2.6 Signaling SpecificationsMost processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling

Datasheet 23Electrical SpecificationsNOTES:1. Refer to Section 4.2 for signal descriptions.2. In processor systems where no debug port is implemented

Electrical Specifications24 Datasheet2.6.2 CMOS and Open Drain SignalsLegacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS in

Datasheet 25Electrical SpecificationsNOTE:1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer to Table

Electrical Specifications26 Datasheet2.6.3.1 GTL+ Front Side Bus SpecificationsIn most cases, termination resistors are not required as these are inte

Datasheet 27Electrical Specifications2.7.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the proc

Electrical Specifications28 Datasheet2.7.4 BCLK[1:0] Specifications.Table 17. Front Side Bus Differential BCLK SpecificationsSymbol Parameter Min Typ

Datasheet 29Electrical SpecificationsTable 19. FSB Differential Clock Specifications (1333 MHz FSB)T# Parameter Min Nom Max Unit Figure Notes1NOTES:1.

Datasheet 3Contents1Introduction...91.1 Ter

Electrical Specifications30 Datasheet§ §Figure 4. Differential Clock Crosspoint SpecificationFigure 5. Differential Measurements660 670 680 690 700 71

Datasheet 31Package Mechanical Specifications3 Package Mechanical SpecificationsThe processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) pac

Package Mechanical Specifications32 DatasheetFigure 7. Processor Package Drawing Sheet 1 of 3

Datasheet 33Package Mechanical SpecificationsFigure 8. Processor Package Drawing Sheet 2 of 3

Package Mechanical Specifications34 DatasheetFigure 9. Processor Package Drawing Sheet 3 of 3

Datasheet 35Package Mechanical Specifications3.2 Processor Component Keep-Out ZonesThe processor may contain components on the substrate that define c

Package Mechanical Specifications36 Datasheet3.5 Package Insertion SpecificationsThe processor can be inserted into and removed from a LGA775 socket 1

Datasheet 37Package Mechanical SpecificationsFigure 11. Processor Top-Side Markings Example for 1333 MHz ProcessorsATPOS/NINTEL ©'05 QX6850INTEL

Package Mechanical Specifications38 Datasheet3.9 Processor Land CoordinatesFigure 12 shows the top view of the processor land coordinates. The coordin

Datasheet 39Land Listing and Signal Descriptions4 Land Listing and Signal DescriptionsThis chapter provides the processor land assignment and signal d

4 Datasheet5.2.5 THERMTRIP# Signal...795.3 Platform Environment Control I

Land Listing and Signal Descriptions40 DatasheetFigure 13. land-out Diagram (Top View – Left Side)30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15ANVCC

Datasheet 41Land Listing and Signal DescriptionsFigure 14. land-out Diagram (Top View – Right Side)14 13 12 11 10 9 8 7 6 5 4 3 2 1VCC VSS VCC VCC VSS

Land Listing and Signal Descriptions42 DatasheetTable 23. Alphabetical Land AssignmentsLand NameLand #Signal Buffer TypeDirectionA3# L5 Source Synch I

Land Listing and Signal DescriptionsDatasheet 43D18# F9 Source Synch Input/OutputD19# E9 Source Synch Input/OutputD20# D7 Source Synch Input/OutputD21

Land Listing and Signal Descriptions44 DatasheetFC32 H15 Power/OtherFC33 H16 Power/OtherFC34 J17 Power/OtherFC35 H4 Power/OtherFC36 AD3 Power/OtherFC3

Land Listing and Signal DescriptionsDatasheet 45TRDY# E3 Common Clock InputTRST# AG1 TAP InputVCC AA8 Power/Other VCC AB8 Power/Other VCC AC23 Power

Land Listing and Signal Descriptions46 DatasheetVCC AJ18 Power/Other VCC AJ19 Power/Other VCC AJ21 Power/Other VCC AJ22 Power/Other VCC AJ25 Power

Land Listing and Signal DescriptionsDatasheet 47VCC J28 Power/Other VCC J29 Power/Other VCC J30 Power/Other VCC J8 Power/Other VCC J9 Power/Other

Land Listing and Signal Descriptions48 DatasheetVID_SELECT AN7 Power/Other OutputVID0 AM2 Power/Other OutputVID1 AL5 Power/Other OutputVID2 AM3 Power

Land Listing and Signal DescriptionsDatasheet 49VSS AG20 Power/Other VSS AG23 Power/Other VSS AG24 Power/Other VSS AG7 Power/Other VSS AH1 Power/O

Datasheet 5Figures1VCC Static and Transient Tolerance...202VCC Overshoot Exa

Land Listing and Signal Descriptions50 DatasheetVSS B20 Power/Other VSS B24 Power/Other VSS B5 Power/Other VSS B8 Power/Other VSS C10 Power/Other

Land Listing and Signal DescriptionsDatasheet 51VSS N3 Power/Other VSS N6 Power/Other VSS N7 Power/Other VSS P23 Power/Other VSS P24 Power/Other

Land Listing and Signal Descriptions52 DatasheetTable 24. Numerical Land AssignmentLand #Land NameSignal Buffer TypeDirectionA2 VSS Power/Other A3 RS

Land Listing and Signal DescriptionsDatasheet 53C20 DBI3# Source Synch Input/OutputC21 D58# Source Synch Input/OutputC22 VSS Power/Other C23 VCCIOPLL

Land Listing and Signal Descriptions54 DatasheetF11 D23# Source Synch Input/OutputF12 D24# Source Synch Input/OutputF13 VSS Power/Other F14 D28# Sour

Land Listing and Signal DescriptionsDatasheet 55H30 BSEL1 Power/Other OutputJ1 VTT_OUT_LEFT Power/Other OutputJ2 FC3 Power/OtherJ3 FC22 Power/Other J

Land Listing and Signal Descriptions56 DatasheetM30 VCC Power/Other N1 PWRGOOD Power/Other InputN2 IGNNE# Asynch CMOS InputN3 VSS Power/Other N4 RES

Land Listing and Signal DescriptionsDatasheet 57U28 VCC Power/Other U29 VCC Power/OtherU30 VCC Power/Other V1 MSID1 Power/Other OutputV2 RESERVEDV3

Land Listing and Signal Descriptions58 DatasheetAB26 VSS Power/Other AB27 VSS Power/Other AB28 VSS Power/Other AB29 VSS Power/Other AB30 VSS Power

Land Listing and Signal DescriptionsDatasheet 59AF12 VCC Power/Other AF13 VSS Power/Other AF14 VCC Power/Other AF15 VCC Power/Other AF16 VSS Power

6 DatasheetTables1 References ...112 Voltag

Land Listing and Signal Descriptions60 DatasheetAH30 VCC Power/Other AJ1 BPM1# Common Clock Input/OutputAJ2 BPM0# Common Clock Input/OutputAJ3 ITP_CL

Land Listing and Signal DescriptionsDatasheet 61AL18 VCC Power/Other AL19 VCC Power/Other AL20 VSS Power/Other AL21 VCC Power/Other AL22 VCC Power

Land Listing and Signal Descriptions62 Datasheet4.2 Alphabetical Signals ReferenceTable 25. Signal Description (Sheet 1 of 9)Name Type DescriptionA[3

Datasheet 63Land Listing and Signal DescriptionsBPM[5:0]#BPMb[3:0]#Input/OutputBPM[5:0]# and BPMb[3:0]# (Breakpoint Monitor) are breakpoint and perfor

Land Listing and Signal Descriptions64 DatasheetD[63:0]#Input/OutputD[63:0]# (Data) are the data signals. These signals provide a 64-bit data path bet

Datasheet 65Land Listing and Signal DescriptionsDEFER# InputDEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-orde

Land Listing and Signal Descriptions66 DatasheetHIT#HITM#Input/OutputInput/OutputHIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop op

Datasheet 67Land Listing and Signal DescriptionsLOCK#Input/OutputLOCK# indicates to the system that a transaction must occur atomically. This signal m

Land Listing and Signal Descriptions68 DatasheetRS[2:0]# InputRS[2:0]# (Response Status) are driven by the response agent (the agent responsible for c

Datasheet 69Land Listing and Signal DescriptionsTHERMTRIP# OutputIn the event of a catastrophic cooling failure, the processor will automatically shut

Datasheet 7Revision History§Revision NumberDescription Date-001 • Initial release November 2006-002• Added specifications for the Intel® Core™2 Quad P

Land Listing and Signal Descriptions70 Datasheet§ §VRDSEL InputThis input should be left as a no connect in order for the processor to boot. The proce

Datasheet 71Thermal Specifications and Design Considerations5 Thermal Specifications and Design Considerations5.1 Processor Thermal SpecificationsThe

Thermal Specifications and Design Considerations72 DatasheetThe case temperature is defined at the geometric top center of the processor. Analysis ind

Datasheet 73Thermal Specifications and Design ConsiderationsTable 27. Thermal Profile for 130 W ProcessorsPower (W)Maximum Tc (°C)Power (W)Maximum Tc

Thermal Specifications and Design Considerations74 DatasheetTable 28. Thermal Profile for 105 W ProcessorsPower (W)Maximum Tc (°C)Power (W)Maximum Tc

Datasheet 75Thermal Specifications and Design ConsiderationsTable 29. Thermal Profile 95 W ProcessorsPower (W)Maximum Tc (°C)Power (W)Maximum Tc (°C)P

Thermal Specifications and Design Considerations76 Datasheet5.1.2 Thermal MetrologyThe maximum and minimum case temperatures (TC) for the processor is

Datasheet 77Thermal Specifications and Design Considerationsunder-designed thermal solution that is not able to prevent excessive activation of the TC

Thermal Specifications and Design Considerations78 DatasheetThe PROCHOT# signal is asserted when a high temperature situation is detected, regardless

Datasheet 79Thermal Specifications and Design Considerations5.2.4 PROCHOT# SignalAn external signal, PROCHOT# (processor hot), is asserted when the pr

8 DatasheetIntel® Core™2 Extreme Quad-Core Processor QX6000 and Intel® Core™2 Quad Processor Q6000 Sequence Features The Intel Core™2 Extreme quad-cor

Thermal Specifications and Design Considerations80 Datasheet5.3 Platform Environment Control Interface (PECI)5.3.1 IntroductionPECI offers an interfac

Datasheet 81Thermal Specifications and Design Considerations5.3.2 PECI Specifications5.3.2.1 PECI Device AddressThe socket 0 PECI register resides at

Thermal Specifications and Design Considerations82 Datasheet

Datasheet 83Features6 Features6.1 Power-On Configuration OptionsSeveral configuration options can be configured by hardware. The processor samples the

Features84 Datasheet6.2.1 Normal StateThis is the normal operating state for the processor.6.2.2 HALT and Extended HALT Powerdown StatesThe processor

Datasheet 85FeaturesThe system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# inter

Features86 Datasheet6.2.4 Extended HALT Snoop or HALT Snoop State,Stop Grant Snoop StateThe Extended HALT Snoop State is used in conjunction with the

Datasheet 87Boxed Processor Specifications7 Boxed Processor SpecificationsThe processor will also be offered as an Intel boxed processor. Intel boxed

Boxed Processor Specifications88 Datasheet7.1 Mechanical Specifications7.1.1 Boxed Processor Cooling Solution DimensionsThis section documents the mec

Datasheet 89Boxed Processor SpecificationsNOTES:1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanica

Datasheet 9Introduction1 IntroductionThe Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel® Core™2 quad processor Q6000 sequence are

Boxed Processor Specifications90 Datasheet7.1.2 Boxed Processor Fan Heatsink WeightThe boxed processor fan heatsink will not weigh more than 550 grams

Datasheet 91Boxed Processor SpecificationsFigure 26. Boxed Processor Fan Heatsink Power Cable Connector DescriptionTable 32. Fan Heatsink Power and Si

Boxed Processor Specifications92 Datasheet7.3 Thermal SpecificationsThis section describes the cooling requirements of the fan heatsink solution used

Datasheet 93Boxed Processor Specifications Figure 28. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)Figure 29. Boxed Process

Boxed Processor Specifications94 Datasheet7.3.2 Fan Speed Control Operation (Intel® Core™2 Extreme processors only)The boxed processor fan heatsink is

Datasheet 95Boxed Processor SpecificationsIf the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the mothe

Boxed Processor Specifications96 DatasheetIf the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header

Datasheet 97Debug Tools Specifications8 Debug Tools Specifications8.1 Logic Analyzer Interface (LAI)Intel is working with two logic analyzer vendors t

Debug Tools Specifications98 Datasheet