Intel E3 Manual de usuario

Intel® Xeon® Processor E3-1200 v3Product FamilyDatasheet – Volume 1 of 2June 2013Order No.: 328907-001

Figure 1. Platform Block DiagramProcessorPCI Express* 3.0Digital Display Interface (DDI)(3 interfaces) System Memory1333 / 1600 MT/s 2 DIMMs / CHCH AC

Symbol Definition and Conditions Min Max Units Notes1VnNegative-Edge ThresholdVoltage0.275 *VCCIO_TERM0.500* VCCIO_TERMV —VpPositive-Edge ThresholdVol

8.0 Package Mechanical SpecificationsThe processor is packaged in a Flip-Chip Land Grid Array package that interfaces withthe motherboard using the L

mechanical system or component testing should not exceed the maximum limits. Theprocessor package substrate should not be used as a mechanical referen

Table 52. Processor MaterialsComponent MaterialIntegrated Heat Spreader (IHS) Nickel Plated CopperSubstrate Fiber Reinforced ResinSubstrate Lands Gold

Figure 22. Processor Package Land Coordinates8.9 Processor Storage SpecificationsThe following table includes a list of the specifications for device

Parameter Description Minimum Maximum NotesRHsustained storageThe maximum device storage relativehumidity for a sustained period of time.60% @ 24 °C 5

9.0 Processor Ball and Signal InformationThis chapter provides processor ball information. The following table provides the balllist by signal name.T

Signal Name Ball #FDI0_TX0N1 C13FDI0_TX0P0 A14FDI0_TX0P1 B13IST_TRIGGER C39IVR_ERROR R36PECI N37PEG_RCOMP P3PEG_RXN0 F15PEG_RXN1 E14PEG_RXN10 F6PEG_RX

Signal Name Ball #RSVD M38RSVD N35RSVD P33RSVD R33RSVD R34RSVD T34RSVD T35RSVD T8RSVD U8RSVD W8RSVD Y8RSVD_TP A4RSVD_TP AV1RSVD_TP AW2RSVD_TP B3RSVD_T

Signal Name Ball #SA_DQ6 AF37SA_DQ60 AG2SA_DQ61 AG3SA_DQ62 AE2SA_DQ63 AE1SA_DQ7 AF40SA_DQ8 AH40SA_DQ9 AH39SA_DQSN0 AE38SA_DQSN1 AJ38SA_DQSN2 AN38SA_DQ

• Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)• PCLMULQDQ Instruction• Intel® Secure Key• Intel® Transactional Synchronization

Signal Name Ball #SB_DQ36 AR13SB_DQ37 AP13SB_DQ38 AM13SB_DQ39 AM12SB_DQ4 AD34SB_DQ40 AR9SB_DQ41 AP9SB_DQ42 AR6SB_DQ43 AP6SB_DQ44 AR10SB_DQ45 AP10SB_DQ

Signal Name Ball #VCC B25VCC B27VCC B29VCC B31VCC B33VCC B35VCC C24VCC C25VCC C26VCC C27VCC C28VCC C29VCC C30VCC C31VCC C32VCC C33VCC C34VCC C35VCC D2

Signal Name Ball #VCC M13VCC M15VCC M17VCC M19VCC M21VCC M23VCC M25VCC M27VCC M29VCC M33VCC M8VCC P8VCC_SENSE E40VCCIO_OUT L40VCOMP_OUT P4VDDQ AJ12VDD

Signal Name Ball #VSS AH36VSS AH4VSS AH5VSS AH8VSS AJ11VSS AJ14VSS AJ16VSS AJ18VSS AJ19VSS AJ22VSS AJ23VSS AJ26VSS AJ27VSS AJ30VSS AJ31VSS AJ32VSS AJ3

Signal Name Ball #VSS AR14VSS AR16VSS AR17VSS AR18VSS AR19VSS AR20VSS AR21VSS AR22VSS AR23VSS AR24VSS AR27VSS AR30VSS AR31VSS AR32VSS AR33VSS AR34VSS

Signal Name Ball #VSS D24VSS D26VSS D28VSS D30VSS D32VSS D34VSS D36VSS D37VSS D5VSS D6VSS D7VSS D9VSS E10VSS E18VSS E20VSS E22VSS E23VSS E3VSS E36VSS

Signal Name Ball #VSS L36VSS L38VSS L6VSS L7VSS L8VSS L9VSS M1VSS M12VSS M14VSS M16VSS M18VSS M20VSS M22VSS M24VSS M26VSS M28VSS M30VSS M32VSS M34VSS

1.4 Thermal Management Support• Digital Thermal Sensor• Adaptive Thermal Monitor• THERMTRIP# and PROCHOT# support• On-Demand Mode• Memory Open and Cl

Term DescriptioneDP Embedded Display PortEPG Electrical Power GatingEU Execution UnitFMA Floating-point fused Multiply Add instructionsFSC Fan Speed C

Term DescriptionNCTFNon-Critical to Function. NCTF locations are typically redundant ground or non-criticalreserved, so the loss of the solder joint c

Term DescriptionTCONTROLTCONTROL is a static value that is below the TCC activation temperature and used as atrigger point for fan speed control. When

Document DocumentNumber / LocationAdvanced Configuration and Power Interface 3.0http://www.acpi.info/PCI Local Bus Specification 3.0http://www.pcisig.

2.0 Interfaces2.1 System Memory Interface• Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM)with a maximum of two DIMMs per

2.1.1 System Memory Technology SupportedThe Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with twoindependent, 64-bit wide channel

RawCardVersionDIMMCapacityDRAMDeviceTechnologyDRAMOrganization# ofDRAMDevices# ofPhysicalDevicesRanks# ofRow / ColAddressBits# ofBanksInsideDRAMPage S

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OROTHERWISE, TO ANY INTELLECTU

Dual-Channel Mode – Intel® Flex Memory Technology ModeThe IMC supports Intel Flex Memory Technology Mode. Memory is divided intosymmetric and asymmetr

2.1.3.1 System Memory FrequencyIn all modes, the frequency of system memory is the lowest frequency of all memorymodules placed in the system, as det

2.2 PCI Express* InterfaceThis section describes the PCI Express* interface capabilities of the processor. See thePCI Express Base* Specification 3.0

• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).• Peer segment destination posted write traffic (no peer-to-peer re

Figure 3. PCI Express* Related Register Structures in the ProcessorPCI-PCI Bridge representing root PCI Express ports (Device 1 and Device 6)PCI Compa

Figure 4. PCI Express* Typical Operation 16 Lanes Mapping01234567891011121314151 X 16ControllerLane 00123456789101112131415Lane 1Lane 2Lane 3Lane 4Lan

• 5 GT/s point-to-point DMI interface to PCH is supported.• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of500 MB

2.4 Processor GraphicsThe processor graphics contains a generation 7.5 graphics core architecture. Thisenables substantial gains in performance and l

Figure 5. Processor Graphics Controller Unit Block Diagram2.5.1 3D and Video Engines for Graphics ProcessingThe Gen 7.5 3D engine provides the follow

Vertex Shader (VS) StageThe VS stage performs shading of vertices output by the VF function. The VS unitproduces an output vertex reference for every

ContentsRevision History...81.0 Introdu

Logical 128-Bit Fixed BLT and 256 Fill EngineThis BLT engine accelerates the GUI of Microsoft Windows* operating systems. The128-bit BLT engine provid

• The HDMI* interface supports HDMI with 3D, 4K, Deep Color, and x.v.Color. TheDisplayPort* interface supports the VESA DisplayPort* Standard Version

• Organizing pixels into frames• Optionally scaling the image to the desired size• Re-timing data for the intended target• Formatting data according t

TMDS data and clock channels. These channels are used to carry video, audio, andauxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used

Embedded DisplayPort*Embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standardoriented towards applications such as notebook and

Table 7. Valid Three Display Configurations through the ProcessorDisplay 1 Display 2 Display 3 MaximumResolution Display1MaximumResolutionDisplay 2Max

2.7 Intel® Flexible Display Interface (Intel® FDI)• The Intel Flexible Display Interface (Intel FDI) passes display data from theprocessor (source) t

Figure 9. Example for PECI Host-Clients ConnectionVTTHost / OriginatorQ1nXQ21XPECICPECI<10pF/NodeQ3nXVTTPECI ClientAdditional PECI ClientsInterface

3.0 TechnologiesThis chapter provides a high-level description of Intel technologies implemented in theprocessor.The implementation of the features m

• More reliable: Due to the hardware support, VMMs can now be smaller, lesscomplex, and more efficient. This improves reliability and availability and

4.2 Processor Core Power Management... 504.2.1 Enhanced Intel® SpeedStep® Techno

• Descriptor-Table Exiting— Descriptor-table exiting allows a VMM to protect a guest OS from internal(malicious software based) attack by preventing r

Figure 10. Device to Domain Mapping StructuresRoot entry 0Root entry NRoot entry 255Context entry 0Context entry 255Context entry 0Context entry 255(B

• Memory controller and processor graphics comply with the Intel VT-d 1.2Specification.• Two Intel VT-d DMA remap engines.— iGFX DMA remap engine— Def

Another aspect of the trust decision is the ability of the platform to resist attempts tochange the controlling environment. The Intel TXT platform wi

Intel recommends enabling Intel HT Technology with Microsoft Windows* 8 andMicrosoft Windows* 7 and disabling Intel HT Technology using the BIOS for a

digital signal processing software. FMA improves performance in face detection,professional imaging, and high performance computing. Gather operations

performance of fine-grain locking while actually programming using coarse-grainlocks. Details on Intel TSX may be found in Intel® Architecture Instruc

• The semantics for accessing APIC registers have been revised to simplify theprogramming of frequently-used APIC registers by system software. Specif

4.0 Power ManagementThis chapter provides information on the following power management topics:• Advanced Configuration and Power Interface (ACPI) St

4.1 Advanced Configuration and Power Interface (ACPI)States SupportedThis section describes the ACPI states supported by the processor.Table 9. Syste

6.14 Processor Internal Pull-Up / Pull-Down Terminations... 857.0 Electrical Specifications...

Table 13. Direct Media Interface (DMI) StatesState DescriptionL0 Full on – Active transfer state.L0s First Active Power Management low power state – L

• Multiple frequency and voltage points for optimal performance and powerefficiency. These operating points are known as P-states.• Frequency selectio

Figure 13. Thread and Core C-State Entry and ExitC1 C1E C7C6C3C0MWAIT(C1), HLTC0MWAIT(C7),P_LVL4 I/O ReadMWAIT(C6),P_LVL3 I/O ReadMWAIT(C3),P_LVL2 I/O

Note: When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. TheMWAIT sub-state is always zero if I/O MWAIT redirection is used.

Core C6 StateIndividual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read oran MWAIT(C6) instruction. Before entering core C6 s

— For package C-states, the processor is not required to enter C0 state beforeentering any other C-state.— Entry into a package C-state may be subject

Figure 14. Package C-State Entry and ExitC0C1C6C7C3Package C0 StateThis is the normal operating state for the processor. The processor remains in then

Package C2 StatePackage C2 state is an internal processor state that cannot be explicitly requested bysoftware. A processor enters Package C2 state wh

Note: Package C6 state is the deepest C-state supported on discrete graphics systems withPCI Express Graphics (PEG).Package C7 state is the deepest C

2. Active power-down (APD): This mode is entered if there are open pages when de-asserting CKE. In this mode the open pages are retained. Power-saving

Tables1 Terminology... 122 Related Documents..

4.3.2.2 Conditional Self-RefreshDuring S0 idle state, system memory may be conditionally placed into self-refreshstate when the processor is in packa

4.3.4 DDR Electrical Power Gating (EPG)The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while theprocessor is at C3 or deeper

package, and the application demand for additional processor or graphicsperformance. The processor core control is maintained by an embedded controlle

5.0 Thermal ManagementThis chapter provides both component-level and system-level thermal management.Topics convered include processor thermal specif

5.1 Thermal MetrologyThe maximum Thermal Test Vehicle (TTV) case temperatures (TCASE-MAX) can bederived from the data in the appropriate TTV thermal

The ΨCA point at DTS = -1 defines the minimum ΨCA required at TDP considering theworst case system design TAMBIENT design point:ΨCA = (TCASE-MAX – TAM

Table 18. Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance AboveTCONTROLProcessorTDPΨCA at DTS =TCONTROL1, 2At System TAMBIENT-MAX = 30 °

Figure 17. Digital Thermal Sensor (DTS) Thermal Profile DefinitionTable 19. Thermal Margin SlopePCG DieConfiguration(Native)Core + GTTDP (W) TCC Activ

Performance TargetsThe following table provides boundary conditions and performance targets as guidancefor thermal solution design. Thermal solutions

Processor PCG2PackageTDP3PlatformTDP4Heatsink5TLA,Airflow,RPM,ѰCA6MaximumTCASEThermalProfile7TCASE-MAX @PlatformTDP82C/GT2 35 W12013A35 W 35 WActive S

53 Processor Storage Specifications... 10454 Processor Ball List by Signal

method to use on a dynamic basis. BIOS is not required to select a specific method(as with previous-generation processors supporting TM1 or TM2). The

A small amount of hysteresis has been included to prevent rapid active/inactivetransitions of the TCC when the processor temperature is near the TCC a

PROCHOT# SignalAn external signal, PROCHOT# (processor hot), is asserted when the processor coretemperature has exceeded its specification. If Adaptiv

Error and Thermal Protection Signals on page 83). THERMTRIP# activation isindependent of processor activity. The temperature at which THERMTRIP# asser

5.9 Intel® Turbo Boost Technology Thermal ConsiderationsIntel Turbo Boost Technology allows processor cores and integrated graphics cores torun faste

5.9.2 Package Power ControlThe package power control allows for customization to implement optimal turbo withinplatform power delivery and package th

Power_Limit_2 for up to approximately 1.5 the Turbo Time Parameter. See theappropriate processor Thermal Mechanical Design Guidelines for more informa

6.0 Signal DescriptionThis chapter describes the processor signals. They are arranged in functional groupsaccording to their associated interface or

Signal Name Description Direction / BufferTypeSA_DQ[63:0]Data Bus: Channel A data signal interface to the SDRAM databus.I/ODDR3/DDR3LSA_ECC_CB[7:0]ECC

Signal Name Description Direction / BufferTypeSB_CKE[3:0]Clock Enable: (1 per rank). These signals are used to:• Initialize the SDRAMs during power-up

Revision HistoryRevision Description Date001 • Initial Release June 2013Processor—Revision HistoryIntel® Xeon® Processor E3-1200 v3 Product FamilyData

6.3 Reset and Miscellaneous SignalsTable 26. Reset and Miscellaneous SignalsSignal Name Description Direction /Buffer TypeCFG[19:0]Configuration Sign

Signal Name Description Direction /Buffer TypeSM_DRAMRST#DRAM Reset: Reset signal from processor to DRAM devices. Onesignal common to all channels.OCM

6.6 Direct Media Interface (DMI)Table 29. Direct Media Interface (DMI) – Processor to PCH Serial InterfaceSignal Name Description Direction / BufferT

Signal Name Description Direction / BufferTypeTDOTest Data Out: This signal transfers serial test data outof the processor. This signal provides the s

6.10 Power SequencingTable 33. Power SequencingSignal Name Description Direction / BufferTypeSM_DRAMPWROKSM_DRAMPWROK Processor Input: This signalcon

6.13 Ground and Non-Critical to Function (NCTF) SignalsTable 36. Ground and Non-Critical to Function (NCTF) SignalsSignal Name Description Direction

7.0 Electrical SpecificationsThis chapter provides the processor electrical specifications including integratedvoltage regulator (VR), VCC Voltage Id

Table 38. VR 12.5 Voltage IdentificationBit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC0 0 0 0 0 0 0 0 00h 0.00000 0 0 0 0 0 0 1 01h 0.50000 0 0 0 0 0 1 0 02h

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC0 1 0 0 0 0 1 0 42h 1.15000 1 0 0 0 0 1 1 43h 1.16000 1 0 0 0 1 0 0 44h 1.17000 1 0 0 0 1 0 1 45h 1.18000 1 0 0

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC1 0 0 0 0 1 1 0 86h 1.83001 0 0 0 0 1 1 1 87h 1.84001 0 0 0 1 0 0 0 88h 1.85001 0 0 0 1 0 0 1 89h 1.86001 0 0 0

1.0 IntroductionThe Intel® Xeon® processor E3-1200 v3 product family are 64-bit, multi-coreprocessors built on 22-nanometer process technology.The pr

Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0Hex VCC1 1 0 0 1 0 1 0 CAh 2.51001 1 0 0 1 0 1 1 CBh 2.52001 1 0 0 1 1 0 0 CCh 2.53001 1 0 0 1 1 0 1 CDh 2.54001 1 0 0

7.4 Reserved or Unused SignalsThe following are the general types of reserved (RSVD) signals and connectionguidelines:• RSVD – these signals should n

Signal Group Type SignalsSingle ended CMOS Output SM_DRAMRST#DDR3/DDR3L Data Signals 2Single ended DDR3/DDR3L Bi-directionalSA_DQ[63:0], SB_DQ[63:0]Di

Signal Group Type SignalsOther SKTOCC#, PCI Express* GraphicsDifferential PCI Express Input PEG_RXP[15:0], PEG_RXN[15:0]Differential PCI Express Outpu

7.8 Voltage and Current SpecificationsTable 40. Processor Core Active and Idle Mode DC Voltage and Current SpecificationsSymbol Parameter Min Typ Max

Symbol Parameter Min Typ Max Unit Note1PMAX2013D PCGPMAX— — 153 W 9PMAX2013C PCGPMAX— — 121 W 9PMAX2013B PCGPMAX— — 99 W 9PMAX2013A PCGPMAX— — 83 W 9N

Table 42. VCCIO_OUT, VCOMP_OUT, and VCCIO_TERMSymbol Parameter Typ Max Units NotesVCCIO_OUTTerminationVoltage1.0— VICCIO_OUT MaximumExternal Load— 300

Symbol Parameter Min Typ Max Units Notes1RON_DN(CTL)DDR3/DDR3L ControlBuffer pull-downResistance1925 31 Ω 5, 11,13RON_UP(RST)DDR3/DDR3L ResetBuffer pu

Table 45. Embedded DisplayPort* (eDP) Group DC SpecificationsSymbol Parameter Min Typ Max UnitsVILHPD Input Low Voltage 0.02 — 0.21 VVIHHPD Input High

Symbol Parameter Min Max Units Notes1VIHInput High Voltage (other GTL) VCCIO_TERM * 0.72 — V 2, 4RONBuffer on Resistance (CFG/BPM) 16 24 Ω —RONBuffer