Intel I5 Manual de usuario descargar pdf (Pagina 55)

Specification Update 55

Documentation Changes

The Documentation Changes listed in this section apply to the following documents:

•Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 1: Basic

Architecture

•Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 2A:

Instruction Set Reference Manual A-M

•Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 2B:

Instruction Set Reference Manual N-Z

•Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:

System Programming Guide

•Intel

64 and IA-32 Architectures Software Developer’s Manual, Volume 3B:

System Programming Guide

All Documentation Changes will be incorporated into a future version of the appropriate

Processor documentation.

Note: Documentation changes for Intel

64 and IA-32 Architecture Software Developer's

Manual volumes 1, 2A, 2B, 3A, and 3B will be posted in a separate document, Intel

and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow

the link below to become familiar with this file.

http://developer.intel.com/products/processor/manuals/index.htm

There are no new Documentation Changes in this Specification Update revision.

BU1. On-Demand Clock Modulation Feature Clarification

Software Controlled Clock Modulation section of the Intel

64 and IA-32 Architectures

Software Developer's Manual, Volume 3B: System Programming Guide will be modified

to differentiate On-demand clock modulation feature on different processors. The

clarification will state:

For Hyper-Threading Technology enabled processors, the IA32_CLOCK_MODULATION

modulation feature to work properly, the feature must be enabled on all the logical

processors within a physical processor. If the programmed duty cycle is not identical for

all the logical processors, the processor clock will modulate to the highest duty cycle

programmed for processors if the CPUID DisplayFamily_DisplayModel signatures is

listed in Table 14-2. For all other processors, if the programmed duty cycle is not

identical for all logical processors in the same core, the processor will modulate at the

lowest programmed duty cycle.

For multiple processor cores in a physical package, each core can modulate to a

programmed duty cycle independently.

For the P6 family processors, on-demand clock modulation was implemented through

the chipset, which controlled clock modulation through the processor’s STPCLK# pin.

Table 14-2. CPUID Signatures for Legacy Processors That Resolve to Higher

Performance Setting of Conflicting Duty Cycle Requests

1 2 ... 50 51 52 53 54 55 56

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