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Graphics, Video, and Display
Intel
®
Atom™ Processor E6xx Series Datasheet
96
Table 88. 50h: GVD.MGGC – Graphics Control
Size: 32 bit Default: 00300000h Power Well: Core
Access
PCI Configuration B:D:F 0:2:0
Offset Start:
Offset End:
50h
Message Bus Port:
06h
Register Address: 14h
Bit Range Default Access Acronym Description
31 :23 0 RO RESERVED
22 :20 011b RW
GRAPHICS_MO
DE_SELECT
GMS: This field is used to select the amount of memory pre-allocated to
support the graphics device in VGA (non-linear) and Native (linear)
modes. If graphics is disabled, this value must be programmed to 000h.
000 = No memory pre-allocated. Graphics does not claim VGA cycles
(Mem and IO), and CC.SCC is 80h.
001 = DVMT (UMA) mode, 1 MB of memory pre-allocated for frame
buffer
010 = DVMT (UMA) mode, 4 MB of memory pre-allocated for frame
buffer
011 = DVMT (UMA) mode, 8 MB of memory pre-allocated for frame
buffer
100 = DVMT (UMA) mode, 16 MB of memory pre-allocated for frame
buffer
101 = DVMT (UMA) mode, 32 MB of memory pre-allocated for frame
buffer
110 = DVMT (UMA) mode, 48 MB of memory pre-allocated for frame
buffer
111 = DVMT (UMA) mode, 64 MB of memory pre-allocated for frame
buffer
When GMS not equal to 000 (and VD=0) the GVD will check if the SCL
address scldown3_address[31:0] is in the VGA memory range. (The VGA
memory range is A0000h to BFFFFh.) If there is a match and MSE = 1
and the SCL command is either a MEMRD or MEMWR, the GVD will initiate
an RMdwvgamemen_cr cycle on the RMbus. If the RMbus returns a hit
the GVD will select the command. As well, when 0 the GVD will check if
scldown3_address[15:0] is one of the VGA IO register range. (The VGA
IO range is 03B0h - 03BBh and 03C0h - 03DFh.) If there is a match and
IOSE = 1 and the SCL command is either an IORD or IOWR, the GVD will
initiate a (VGA) register cycle on the RMbus. If the RMbus returns a hit
the GVD will select the command.When GMS is equal to 000, the GVD will
not check if the SCL address is in the VGA memory range or in the VGA
IO register address range. Also, when GMS is set to 3’b000, then
CC[15:8] is changed to 8’h80 from 8’h00.
19 :18 0 RO RESERVED Reserved
17 0b RW VGA_DISABLE
VD: When set, VGA memory or I/O cycles are not claimed, and CC.SCC is
set to 80h. When cleared, VGA memory and I/O cycles are enabled, and
CC.SCC is set to 00h.
When 0 (and GMS not equal to 000), the GVD will check if the SCL
address scldown3_address[31:0] is in the VGA memory range. (The VGA
memory range is A0000h to BFFFFh.) If there is a match and MSE=1 and
the SCL command is either a MEMRD or MEMWR, the GVD will initiate an
RMdwvgamemen_cr cycle on the RMbus. If the RMbus returns a hit the
GVD will select the command. As well, when 0 the GVD will check if
scldown3_address[15:0] is one of the VGA IO register range. (The VGA
IO range is 03B0h - 03BBh and 03C0h - 03DFh.) If there is a match and
IOSE = 1 and the SCL command is either an IORD or IOWR, the GVD will
initiate a (VGA) register cycle on the RMbus. If the RMbus returns a hit
then the command will be claimed by the GVD. When 1, the GVD will not
check if the SCL address is in the VGA memory range or in the VGA IO
register address range. Also, when the field is set 1’b1 and GMS =
3’b000, then CC[15:8] is changed to 8’h80 from 8’h00.
16 :0 00000h RO RESERVED Reserved
- Atom™ Processor E6xx Series 1
- Legal Lines and Disclaimers 2
- Contents 10
- Revision History 21
- Segment dependent PCIe* 23
- 1.1 Terminology 24
- 1.2 Reference Documents 25
- Intel® Atom™ Processor 26
- E6xx Series 26
- 1.3.1 Low-Power Intel 27
- Architecture Core 27
- 1.3.3 Graphics 27
- 1.3.6.1 LVDS Interface 28
- Introduction 29
- 2.0 Signal Description 31
- 2.1 System Memory Signals 32
- 2.2.1 LVDS Signals 33
- 2.3 PCI Express* Signals 35
- 2.4 Intel 35
- Interface Signals 35
- 2.5 LPC Interface Signals 36
- 2.6 SMBus Interface Signals 36
- 2.7 SPI Interface Signals 36
- 2.10 JTAG and Debug Interface 38
- 2.12 General Purpose I/O 42
- 2.13 Functional Straps 42
- 2.14 Power and Ground Signals 43
- 3.0 Pin States 45
- 3.3.1 LVDS Signals 46
- 3.4 PCI Express* Signals 47
- 3.5 Intel 47
- 3.6 LPC Interface Signals 48
- 3.7 SMBus Interface Signals 48
- 3.8 SPI Interface Signals 48
- 3.11 JTAG and Debug Interface 49
- 3.13 General Purpose I/O 50
- 4.0 System Clock Domains 51
- System Clock Domains 52
- 5.1 Address Map 53
- 5.2 Introduction 53
- 5.3 System Memory Map 54
- Figure 3. System Address Map 55
- 5.3.1 I/O Map 56
- 5.4.1.1 Hard Coded IO Access 58
- 5.4.1.2 IO BAR 59
- 5.4.1.4 Memory BAR 59
- 5.4.2.1 PCI Config Space 59
- : 0000h - 0003h 60
- P – Device 3 Interrupt Pin 64
- R – Device 31 Interrupt Route 64
- 5.5.4 General Configuration 67
- Register and Memory Mapping 68
- 6.0 Memory Controller 69
- 6.5 Refresh Mode 70
- 6.7 Supported DRAM Devices 72
- Atom™ Processor E6xx Series 75
- Graphics, Video, and Display 76
- 7.2.3.2 Lighting Stages 77
- 7.2.4 Pixel Processing 78
- 7.2.5 Unified Shader 78
- 7.3.1.1 Encoding Pipeline 79
- 7.3.1.2 Encode Codec Support 80
- 7.4 Video Decode 81
- 7.4.1.1 Motion Compensation 82
- 7.4.1.2 Deblocking 82
- 7.4.1.4 Pixel Format 83
- Controller 84
- 7.5.1.1 Planes 85
- 7.5.1.2 Display Pipes 86
- 7.5.2.1 LVDS Port 87
- 7.5.2.4 SDVO DVI/HDMI 89
- 7.7 Configuration Registers 90
- 8.1.2.1 Sleep State Support 111
- 8.1.2.4 SMI/SCI Generation 112
- VID — Vendor Identification 113
- 8.2.1.3 CMD — PCI Command 114
- 8.2.1.4 PSTS — Primary Status 114
- DID — Device Identification 114
- CMD — PCI Command 114
- 8.2.1.6 CC — Class Code 115
- PSTS — Primary Status 115
- 8.2.1.7 CLS — Cache Line Size 116
- 8.2.1.8 HTYPE — Header Type 116
- PBN — Primary Bus Number 116
- — I/O Limit Address 118
- 8.2.1.21 IPIN — Interrupt Pin 121
- 01 0b RW SE 122
- 8.2.2.4 DCTL — Device Control 124
- 8.2.2.5 DSTS — Device Status 125
- 8.2.2.7 LCTL — Link Control 126
- 8.2.2.8 LSTS — Link Status 126
- 8.2.2.10 SLCTL — Slot Control 127
- 8.2.2.11 SLSTS — Slot Status 128
- 8.2.2.12 RCTL — Root Control 129
- 8.2.2.14 RSTS — Root Status 129
- RCAP — Root Capabilities 129
- 8.2.5 Port Configuration 132
- FD — Functional Disable 135
- PCI Express* 136
- 9.0 Intel 137
- High Definition Audio 137
- 9.2.1 Dock Sequence 138
- 9.2.2 Undock Sequence 139
- 9.3.1 Registers 140
- Table 177. Intel 141
- Control Register 147
- Register 148
- Capability Header Register 156
- 9.3.2.1 Intel 157
- HD Audio 157
- Registers 157
- Table 225. Intel 158
- GCTL – Global Control 162
- (Sheet 2 of 2) 182
- 10.0 LPC Interface (D31:F0) 187
- 10.2.1 ID—Identifiers 188
- 10.2.5 CC—Class Code Register 190
- 10.4 Interrupt Control 195
- 10.4.3 WDTBA-WDT Base Address 196
- 10.5.2 BDE—BIOS Decode Enable 197
- LPC Interface (D31:F0) 200
- 11.0 ACPI Devices 201
- 11.1.5.1 Read Back Command 202
- 11.1.6 Timer Programming 204
- 11.1.7.1 Simple Read 205
- 11.1.7.3 Read Back Command 206
- Capabilities 208
- 11.2.2 Theory Of Operation 210
- 11.2.2.3 Interrupts 211
- 11.3.1 Overview 212
- 11.3.2 I/O Registers 213
- 11.3.3.1 Generating 218
- 11.3.3.2 Acknowledging 218
- 11.3.4.1 ICW1 219
- 11.3.4.2 ICW2 220
- 11.3.4.3 ICW3 220
- 11.3.4.4 ICW4 220
- 11.3.6.1 Fully Nested Mode 220
- 11.3.6.5 Poll Mode 221
- 11.3.7.1 Normal EOI 222
- 11.3.7.2 Automatic EOI 222
- 11.3.8.2 Special Mask Mode 222
- 11.4.1 Memory Registers 223
- 11.4.2 Index Registers 224
- 11.4.4.1 Theory of Operation 226
- 11.4.4.2 EOI 226
- 11.5 Serial Interrupt 227
- 11.5.2 Start Frame 228
- 11.5.3 Data Frames 228
- 11.5.4 Stop Frame 228
- 11.6 Real Time Clock 230
- : Register A 231
- 11.6.4 Update Cycles 233
- 11.6.5 Interrupts 233
- 11.7 General Purpose I/O 234
- 11.7.3.1 Power Wells 240
- 11.7.3.2 SMI# and SCI Routing 240
- 11.7.3.3 Triggering 240
- 11.8 SMBus Controller 241
- 11.8.3 Overview 244
- 11.8.5.1 Clock Stretching 245
- 11.8.5.2 Bus Time Out 246
- 11.9.4 SPI Protocol 247
- 11.9.5 Host Side Interface 249
- SPIA – SPI Address 252
- ACPI Devices 256
- 11.9.5.14 Flash Protection 258
- Control Register. This is 259
- 11.9.6 SPI Clocking 260
- 11.9.7.1 Run Time Updates 261
- 11.9.7.2 BIOS Sector Updates 261
- 11.9.7.3 SPI Initialization 262
- 11.10 Watchdog Timer 263
- 11.10.4 Theory Of Operation 270
- 11.10.4.3 Reload Sequence 271
- 11.10.4.4 Low Power State 271
- 12.0 Absolute Maximum Ratings 273
- 12.1 Absolute Maximum Rating 274
- 13.0 DC Characteristics 275
- 14.1 Package Diagrams 282
- Figure 11. Intel 283
- Figure 12. Intel 284
- Figure 13. Intel 285
- Figure 14. Intel 286
- Figure 15. Intel 287
- Figure 16. Intel 288
- Figure 17. Intel 289
- Table 407. Pin List 290
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Pioneer 3D podręczniki
Instrukcje obsługi i podręczniki użytkownika dla Odbiorniki samochodowe Pioneer 3D.
Dostarczamy 1 pdf podręczników Pioneer 3D do pobrania za darmo według typów dokumentów: Instrukcja Użytkownika
Pioneer 3D Instrukcja Użytkownika (60 strony)
Marka: Pioneer | Kategoria: Car media receivers | Rozmiar: 1.59 MB |
Spis treści
DEH-22UB
1
Connections
11
Installation
13
Français
21
Télécommande
22
ATTENTION
24
PRÉCAUTION
24
Syntoniseur
25
Connexions
30
Dépannage
35
PRECAUCIÓN
41
ADVERTENCIA
44
Sintonizador
45
Conexiones
50
Instalación
52
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