Intel 2760QM Ficha de datos descargar pdf (Pagina 318)

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101

Processor Uncore Configuration Registers

318 Datasheet, Volume 2

9:8 RW 0h

PAM5_LOENABLE: 0E0000h-0E3FFFh Attribute (LOENABLE)

This field controls the steering of read and write cycles that address the BIOS area

from 0E0000h to 0E3FFFh.

00 = DRAM Disabled: All accesses are directed to DMI.

01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.

10 = Write Only: All writes are send to DRAM. Reads are serviced by DMI.

11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.

7:6 RV 0h Reserved

5:4 RW 0h

PAM4_HIENABLE: 0DC000h-0DFFFFh Attribute (HIENABLE)

This field controls the steering of read and write cycles that address the BIOS area

from 0DC000h to 0DFFFFh.

00 = DRAM Disabled: All accesses are directed to DMI.

01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.

10 = Write Only: All writes are send to DRAM. Reads are serviced by DMI.

11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.

3:2 RV 0h Reserved

1:0 RW 0h

PAM4_LOENABLE: 0D8000h-0DBFFFh Attribute (LOENABLE)

This field controls the steering of read and write cycles that address the BIOS area

from 0D8000h to 0DBFFFh.

00 = DRAM Disabled: All accesses are directed to DMI.

01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.

10 = Write Only: All writes are send to DRAM. Reads are serviced by DMI.

11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.

PAM456

Bus: 1 Device: 12 Function: 6 Offset: 44h

Bit Attr

Reset

Value

Description

1 2 ... 313 314 315 316 317 318 319 320 321 322 323 ... 563 564

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